Dynamic bias control in power amplifier
First Claim
1. A method comprising:
- in a first operating mode, driving first signals onto an output terminal using a first Class AB amplifier circuit, wherein the first Class AB amplifier circuit includes a first power transistor that is biased at a first bias current I1 and at a first collector-to-emitter bias voltage V1, wherein the first signals are in a frequency band above one gigahertz, and wherein a second Class AB amplifier circuit is disabled during the first operating mode; and
in a second operating mode, driving second signals onto the output terminal using the second Class AB amplifier circuit, wherein the second Class AB amplifier circuit includes a second power transistor that is biased at a second bias current 12 and at a second collector-to-emitter bias voltage V2, wherein I1>
I2, wherein V1>
V2, wherein the first Class AB amplifier circuit is disabled during the second operating mode, wherein the second signals are in the frequency band above one gigahertz, and wherein the first and second Class AB amplifier circuits are integrated onto a single integrated circuit.
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Abstract
An RF output power amplifier (PA) of a cellular telephone includes first and second Class AB amplifier circuits. If the cellular telephone is to operate in a high power operating mode, then the first amplifier drives the PA output terminal. The power transistor(s) in the first amplifier is/are biased at a first DC current and a first DC voltage so as to optimize efficiency and linearity at high output powers. If the cellular telephone is to operate in a low power operating mode, then the second amplifier drives the output terminal. The power transistor(s) in the second amplifier is/are biased at a second DC current and a second DC voltage so as to optimize efficiency and linearity at low output powers. By sizing the power transistors in the amplifiers appropriately, emitter current densities are maintained substantially equal so that PA power gain is the same in the two operating modes.
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Citations
23 Claims
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1. A method comprising:
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in a first operating mode, driving first signals onto an output terminal using a first Class AB amplifier circuit, wherein the first Class AB amplifier circuit includes a first power transistor that is biased at a first bias current I1 and at a first collector-to-emitter bias voltage V1, wherein the first signals are in a frequency band above one gigahertz, and wherein a second Class AB amplifier circuit is disabled during the first operating mode; and in a second operating mode, driving second signals onto the output terminal using the second Class AB amplifier circuit, wherein the second Class AB amplifier circuit includes a second power transistor that is biased at a second bias current 12 and at a second collector-to-emitter bias voltage V2, wherein I1>
I2, wherein V1>
V2, wherein the first Class AB amplifier circuit is disabled during the second operating mode, wherein the second signals are in the frequency band above one gigahertz, and wherein the first and second Class AB amplifier circuits are integrated onto a single integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A circuit comprising:
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an output terminal; a first amplifier having an input lead and an output lead, the output lead being coupled to the output terminal, wherein the first amplifier includes a first power transistor that is biased at a first bias current I1 and at a first bias voltage V1; a second amplifier having an input lead and an output lead, the output lead being coupled to the output terminal, wherein the second amplifier includes a second power transistor that is biased at a second bias current I2 and at a second bias voltage V2; and an analog multiplexer having an input lead, a first output lead, a second output lead, and a select input lead, wherein if a first digital logic value is present on the select input lead then the analog multiplexer couples a signal on its input lead through the first output lead and onto the input lead of the first amplifier such that the first amplifier drives a power-amplified version of the signal onto the output terminal, wherein if a second digital logic value is present on the select input lead then the analog multiplexer couples the signal on its input lead through the second output lead and onto the input lead of the second amplifier such that the second amplifier drives a power-amplified version of the signal onto the output terminal, wherein the signal on the input lead of the multiplexer is in a frequency band above one gigahertz, wherein I1>
I2, wherein V1>
V2, wherein the first power transistor has a first DC bias current density when the first amplifier is driving the output terminal, wherein the second power transistor has a second DC bias current density when the second amplifier is driving the output terminal, wherein the first and second DC bias current densities are substantially identical. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A power amplifier capable of amplifying signals in a frequency band above one gigahertz with a power gain that varies by less than five dB when an output power of the power amplifier varies over a forty dB range, wherein the power amplifies has an ACPR (Adjacent Channel Power Ratio) of better than −
- 33 dBc for power amplifier output powers up to 26 dBm, and wherein the power amplifier has an average power efficiency (APE) greater than four percent for a WCDMA (Wideband Code Division Multiple Access) output power PDF (Probability Distribution Function).
- View Dependent Claims (22, 23)
Specification