Method and apparatus for verifying a site-dependent wafer

• US 7,729,795 B2
• Filed: 04/09/2008
• Issued: 06/01/2010
• Est. Priority Date: 03/30/2007
• Status: Expired due to Fees

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Winter, Thomas E., Winkler, Mark G.
• Primary Examiner(s): Patel; Ramesh B
• Assistant Examiner(s): Lee; Douglas S
• Application Number:
  US12/100,153
• Publication Number:
  US 20080243297A1
• Time in Patent Office: 783 Days
• Field of Search: 700/109, 700/110, 700/121, 716/4, 716/12, 716/14, 716/19, 703/2, 438/11, 438/5
• US Class Current: 700/121
• CPC Class Codes: G05B 19/41875 characterised by quality surveillance of production
• CPC Class Codes: G05B 2219/31265 Control process by combining history and real time data
• CPC Class Codes: G05B 2219/45031 Manufacturing semiconductor wafers
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
• CPC Class Codes: Y02P 90/80 Management or planning

Abstract

The present invention includes a method of verifying a Site-Dependent (S-D) wafer that includes receiving a first set of S-D wafers by one or more S-D processing elements in one or more processing subsystems, creating a first set of unverified S-D wafers by performing a first S-D creation procedure, establishing S-D wafer state data for each unverified S-D wafer, establishing a first set of evaluation wafers comprising a first number of the unverified S-D wafers, establishing first operational states for a plurality of S-D evaluation elements, determining a first number of available evaluation elements, establishing a first S-D transfer sequence, transferring the first set of S-D evaluation wafers to the first number of available evaluation elements in one or more evaluation subsystems and applying a first corrective action when the number of S-D evaluation wafers is greater than the first number of available evaluation elements.

Claims

1. A method of verifying a Site-Dependent (S-D) wafer comprising:

receiving a first S-D wafer using a Non-Site-Dependent (N-S-D) transfer system;

transferring the first S-D wafer to a first S-D processing element using the N-S-D transfer system;

creating one or more unverified S-D wafers, wherein one or more S-D unverified evaluation features are created at one or more sites on a first S-D unverified wafer using a first S-D creation procedure;

determining a first S-D evaluation wafer using the one or more unverified S-D wafers;

transferring the first S-D evaluation wafer to a first S-D evaluation element using the N-S-D transfer system, or a Site-Dependent (S-D) transfer system, or a combination thereof;

establishing first confidence data for the first S-D evaluation wafer using a first S-D evaluation procedure, wherein a S-D unverified evaluation feature at a first site on the first S-D evaluation wafer is evaluated;

comparing the first confidence data for the first S-D evaluation wafer to first confidence limits;

identifying the first unverified evaluation feature as a high confidence feature having a first level of confidence associated therewith and identifying the first S-D evaluation wafer as a high confidence wafer having the first level of confidence associated therewith, when a first confidence limit is met; and

applying a first corrective action when the first confidence limit is not met.

2. The method of claim 1, wherein the applying a first corrective action comprises:

a) determining a maximum number of evaluation sites on the first S-D evaluation wafer;

b) determining a minimum number of evaluation sites on the first S-D evaluation wafer;

c) creating a first confidence map for the first S-D evaluation wafer;

d) determining a required number of evaluation sites on the first S-D evaluation wafer;

e) selecting a new site on the first S-D evaluation wafer;

f) establishing new confidence data for the first S-D evaluation wafer using a new S-D evaluation procedure, wherein a S-D unverified evaluation feature at the new site on first S-D wafer is evaluated;

g) adding the new site to the first confidence map for the first S-D evaluation wafer;

h) comparing the new confidence data to new first confidence limits for the first S-D evaluation wafer;

i) identifying the S-D unverified evaluation feature at the new site on the first S-D evaluation wafer as a new high confidence feature having a new first level of confidence associated therewith, identifying the first S-D evaluation wafer as a high confidence wafer having the new first level of confidence associated therewith when a new first confidence limit is met;

j) identifying the S-D unverified evaluation feature at the new site on the first S-D evaluation wafer as a new unverified feature having the new confidence data associated therewith, decreasing a number of required sites by one, and increasing a number of visited sites by one, when the new first confidence limit is not met;

k) repeating steps e)-j) when the number of required sites on the first S-D evaluation wafer is greater than zero; and

l) stopping an evaluation of the first S-D evaluation wafer when the number of required sites on the first S-D evaluation wafer is equal to zero.

3. The method of claim 1, wherein the applying the first corrective action comprises:

a1) receiving an additional S-D wafer using the N-S-D transfer system, or the S-D transfer system, or a combination thereof;

b1) transferring the additional S-D wafer to an additional first S-D processing element using the N-S-D transfer system, or the S-D transfer system, or a combination thereof;

c1) creating one or more additional unverified S-D wafers, wherein one or more S-D unverified evaluation features are created at one or more sites on each additional S-D unverified wafer using the first S-D creation procedure;

d1) determining an additional S-D evaluation wafer using the additional unverified S-D wafers;

e1) transferring the additional S-D wafer to an additional first S-D evaluation element using the S-D transfer system;

f1) establishing additional first confidence data for the additional S-D evaluation wafer using an additional first S-D evaluation procedure, wherein a S-D unverified evaluation feature at a first site on the additional S-D evaluation wafer is evaluated;

g1) comparing the additional first confidence data to additional first confidence limits for the additional S-D wafer;

h1) identifying the S-D unverified evaluation feature at the first site on the additional S-D evaluation wafer as an additional high confidence feature having an additional first level of confidence associated therewith and identifying the additional S-D evaluation wafer as a high confidence wafer having the additional first level of confidence associated therewith, when an additional first confidence limit is met; and

i1) applying a second corrective action when the additional first confidence limit is not met.

4. The method of claim 3, wherein the applying a second corrective action comprises:

a2) determining a maximum number of evaluation sites on the additional S-D evaluation wafer;

b2) determining a minimum number of evaluation sites on the additional S-D evaluation wafer;

c2) creating a first confidence map for the additional S-D evaluation wafer;

d2) determining a required number of evaluation sites on the additional S-D evaluation wafer;

e2) selecting a new site on the additional S-D evaluation wafer;

f2) establishing new additional confidence data for the additional S-D evaluation wafer using an additional new S-D evaluation procedure, wherein a S-D unverified evaluation feature at the new site on the additional S-D wafer is evaluated;

g2) adding the new site to the first confidence map for the additional S-D evaluation wafer;

h2) comparing the new additional confidence data to new first confidence limits for the additional S-D evaluation wafer;

i2) identifying the S-D unverified evaluation feature at the new site on the additional S-D evaluation wafer as an additional new high confidence feature having an additional new first level of confidence associated therewith, identifying the first S-D evaluation wafer as a high confidence wafer having the additional new level of confidence associated therewith when an additional new confidence limit is met;

j2) identifying the S-D unverified evaluation feature at the new site on the additional S-D evaluation wafer as an additional new unverified feature having the new additional confidence data associated therewith, decreasing a number of required sites by one, and increasing a number of visited sites by one, when the additional new confidence limit is not met;

k2) repeating steps e2)-j2) when the number of required sites on the additional S-D evaluation wafer is greater than zero; and

l2) stopping an evaluation of the additional S-D evaluation wafer when the number of required sites is equal to zero.

5. The method of claim 1, wherein the applying a first corrective action comprises:

determining a first number of delayed S-D wafers using a first difference between a first number of S-D evaluation wafers and a first number of available evaluation elements; and

storing the first number of delayed S-D wafers for a first period of time using one or more transfer elements in the N-S-D transfer system or the S-D transfer system, or a combination thereof, wherein each transfer element comprises means for supporting two or more wafers.

6. The method of claim 1, wherein the applying a first corrective action comprises:

determining a first number of delayed S-D wafers using a first difference between a first number of S-D evaluation wafers and a first number of available evaluation elements; and

delaying the first number of delayed S-D wafers for a first period of time using one or more transfer elements in the N-S-D transfer system or the S-D transfer system, or a combination thereof, wherein each transfer element comprises means for supporting two or more wafers.

7. The method of claim 1, wherein the applying a first corrective action comprises:

determining a first number of delayed S-D wafers using a first difference between a first number of S-D evaluation wafers and a first number of available evaluation elements;

determining updated S-D wafer state data for a first delayed S-D evaluation wafer;

determining updated operational state data for the one or more S-D evaluation elements in a first evaluation subsystem;

determining a first updated transfer sequence for the first delayed S-D evaluation wafer;

identifying one or more newly-available S-D evaluation elements using the updated operational state data;

transferring the first delayed S-D evaluation wafer to a first newly-available S-D evaluation element in the one or more evaluation subsystems using the first updated transfer sequence when a first newly-available S-D evaluation element is available; and

applying a second corrective action when the first newly-available S-D evaluation element is not available.

8. The method of claim 1, wherein the applying a first corrective action comprises at least one of stopping a processing, pausing the processing, re-evaluating one or more of the S-D evaluation wafers, re-measuring one or more of the S-D evaluation wafers, re-inspecting one or more of the S-D evaluation wafers, re-working one or more of the S-D evaluation wafers, storing one or more of the S-D evaluation wafers, cleaning one or more of the S-D evaluation wafers, delaying one or more of the S-D evaluation wafers, or stripping one or more of the S-D evaluation wafers, or any combination thereof.

9. The method of claim 1, further comprising:

calculating S-D risk assessment maps for the unverified S-D wafers, a first S-D risk assessment map including risk assessment data for the one or more unverified evaluation features created at a first number of evaluation sites on each of the unverified S-D wafers; and

establishing the first set of S-D evaluation wafers using the S-D risk assessment maps for the unverified S-D wafers.

10. The method of claim 2, further comprising:

calculating S-D risk assessment maps for the unverified S-D wafers, a first S-D risk assessment map including risk assessment data for the one or more unverified evaluation features created at a first number of evaluation sites on each of the unverified S-D wafers;

decreasing the number of required evaluation sites by one or more when one or more values in the first S-D risk assessment map are within a first risk assessment limit; and

increasing the number of required evaluation sites by one or more when one or more values in the first S-D risk assessment map are not within the first risk assessment limit.

11. The method of claim 2, further comprising:

calculating S-D damage-assessment maps for the unverified S-D wafers, a first S-D damage-assessment map including damage-assessment data for the one or more unverified evaluation features created at a first number of evaluation sites on each of the unverified S-D wafers;

decreasing the number of required evaluation sites by one or more when one or more values in the first S-D damage-assessment map are within a first damage-assessment limit; and

increasing the number of required evaluation sites by one or more when one or more values in the first S-D risk assessment map are not within the first damage-assessment limit.

12. The method of claim 1, wherein a S-D evaluation library data comprises goodness of fit data, creation rules data, S-D measurement data, S-D inspection data, S-D verification data, S-D mapping data, S-D confidence data, S-D accuracy data, S-D process data, or S-D uniformity data, or any combination thereof.

13. The method of claim 1, further comprising:

determining a first set of N-S-D wafers to be unverified using a first N-S-D processing sequence, wherein the first N-S-D processing sequence comprises one or more N-S-D procedures; and

transferring the first set of N-S-D wafers to one or more first N-S-D processing elements in one or more first subsystems using the N-S-D transfer system or the S-D transfer system, or a combination thereof, the first N-S-D processing sequence being used to determine the one or more first N-S-D processing elements in the one or more first subsystems.

14. The method of claim 1, wherein the first S-D processing element comprises at least one of one or more S-D lithography-related processing elements, one or more S-D scanner-related processing elements, one or more S-D inspection-related processing elements, one or more S-D measurement-related elements, one or more S-D evaluation-related elements, one or more S-D etch-related processing elements, one or more S-D deposition-related processing elements, one or more S-D thermal processing elements, one or more S-D coating-related processing elements, one or more S-D alignment-related processing elements, one or more S-D polishing-related processing elements, one or more S-D storage-related elements, one or more S-D transfer elements, one or more S-D cleaning-related processing elements, one or more S-D rework-related processing elements, one or more S-D oxidation-related processing elements, one or more S-D nitridation-related processing elements, or one or more S-D external processing elements, or any combination thereof.

15. The method of claim 1, wherein the first S-D creation procedure comprises at least one of one or more S-D lithography-related procedures, one or more S-D scanner-related procedures, one or more S-D inspection-related procedures, one or more S-D measurement-related procedures, one or more S-D evaluation-related procedures, one or more S-D etch-related procedures, one or more S-D deposition-related procedures, one or more S-D thermal processing procedures, one or more S-D coating-related procedures, one or more S-D alignment-related procedures, one or more S-D polishing-related procedures, one or more S-D storage-related procedures, one or more S-D transfer procedures, one or more S-D cleaning-related procedures, one or more S-D rework-related procedures, one or more S-D oxidation-related procedures, one or more S-D nitridation-related procedures, or one or more S-D external procedures, or any combination thereof.

16. The method of claim 2, wherein different confidence levels are established for a first confidence value using different magnitude values for a first wafer-verify difference.

17. The method of claim 1, further comprising:

creating the one or more unverified S-D wafers using a mask layer deposition procedure, wherein one or more S-D wafer-verification features are created at one or more sites in a masking layer on each of the unverified S-D wafers, and wherein the first S-D processing element is lithography-related.

18. The method of claim 1, further comprising:

creating the one or more unverified S-D wafers using a mask exposure procedure, wherein one or more S-D wafer-verification features are created at one or more sites in an exposed masking layer on each of the unverified S-D wafers, and wherein the first S-D processing element is scanner-related.

19. The method of claim 1, further comprising:

creating the one or more unverified S-D wafers using a mask development procedure, wherein one or more S-D wafer-verification features are created at one or more sites in a developed masking layer on each of the unverified S-D wafers, and wherein the first S-D processing element is lithography-related.

20. The method of claim 1, further comprising:

creating the one or more unverified S-D wafers using an etching procedure, wherein one or more S-D wafer-verification features are created at one or more sites in one or more etched layers on each of the unverified S-D wafers, and wherein the first S-D processing element is lithography-related.