Compactor independent direct diagnosis of test hardware

• US 7,729,884 B2
• Filed: 11/04/2005
• Issued: 06/01/2010
• Est. Priority Date: 03/31/2004
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Huang, Yu, Rajski, Janusz, Cheng, Wu-Tung
• Primary Examiner(s): Dunn; Drew A
• Assistant Examiner(s): Le; Toan M
• Application Number:
  US11/267,221
• Publication Number:
  US 20060111873A1
• Time in Patent Office: 1,670 Days
• Field of Search: 702/185, 702107-109, 702/117, 702182-183, 702/57, 702 81- 82, 702/85, 702/119, 714/25, 714/30, 714/700, 714726-727, 714/729, 714732-735, 714741-742, 714737-739, 714/799, 703 13- 15
• US Class Current: 702/185
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received including entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.

Claims

1. A computer-implemented method for diagnosing faulty scan cells in a circuit-under-test, comprising:

receiving information indicative of at least compressed test responses to chain patterns and compressed test responses to scan patterns, the compressed test responses to chain patterns and the compressed test responses to scan patterns having been output from a compactor coupled to a circuit-under-test;

identifying a faulty scan chain in the circuit-under-test based at least in part on the information indicative of the compressed test responses to chain patterns;

identifying one or more faulty scan cell candidates in the faulty scan chain based at least in part on the information indicative of the compressed test responses to scan patterns; and

reporting the one or more faulty scan cell candidates identified.

2. The method of claim 1, wherein the information received comprises a failure log.

3. The method of claim 1, wherein the act of identifying the one or more faulty scan cell candidates comprises:

simulating failures in possible faulty scan cell candidates, the simulation incorporating a transformation function performed by the compactor; and

comparing simulation results to the compressed test responses to scan patterns.

4. The method of claim 3, wherein the simulation simulates failing scan patterns and passing scan patterns, and wherein the information received includes information indicative of corresponding failing compressed test responses and passing compressed test responses.

5. The method of claim 3, wherein the simulation incorporates the transformation function by representing the compactor as a mathematical function and applying the mathematical function to simulated uncompressed test responses.

6. The method of claim 3, wherein the simulation incorporates the transformation function by simulating the failures in a circuit representation of the circuit-under-test that has been modified to embed the transformation function.

7. The method of claim 1, wherein the act of identifying the faulty scan chain comprises applying a mathematical function representative of the compactor to one or more of the compressed test responses to chain patterns.

8. The method of claim 1, wherein the act of identifying the faulty scan chain comprises comparing one or more of the compressed test responses to chain patterns to entries in a fault dictionary.

9. The method of claim 1, wherein the information received includes information indicative of test responses to masking chain patterns, the method further comprising determining whether the source of a fault is a scan chain defect or a compression hardware defect based at least in part on the information indicative of the test responses to the masking chain patterns.

10. The method of claim 1, further comprising identifying a fault type in the faulty scan chain based at least in part on the information indicative of the compressed test responses to chain patterns.

11. One or more computer-readable media made according to a method, the method comprising:

receiving information indicative of at least compressed test responses to chain patterns and compressed test responses to scan patterns, the compressed test responses to chain patterns and the compressed test responses to scan patterns having been output from a compactor coupled to a circuit-under-test;

identifying a faulty scan chain in the circuit-under-test based at least in part on the information indicative of the compressed test responses to chain patterns;

identifying one or more faulty scan cell candidates in the faulty scan chain based at least in part on the information indicative of the compressed test responses to scan patterns; and

storing on the one or more computer-readable media the one or more faulty scan cell candidates identified.

12. A method of testing an integrated circuit, comprising:

testing scan chains of a circuit-under-test using multiple chain patterns, wherein the testing comprises,

applying at least one of the chain patterns to the scan chains through a decompressor and a compactor coupled to the scan chains, and

applying at least one of the chain patterns to the scan chains while bypassing the decompressor and the compactor; and

determining whether a fault exists in the scan chains of the circuit-under-test or in the decompressor or the compactor based at least in part on test responses to the chain patterns applied during the testing.

13. The method of claim 12, wherein a fault is determined to exist in the scan chains of the circuit-under-test if a respective chain pattern applied through the decompressor and the compactor and a respective chain pattern bypassing the decompressor and the compactor both produce faulty test responses.

14. The method of claim 12, wherein a fault is determined to exist in the decompressor or the compactor if a respective chain pattern applied through the decompressor and the compactor produces a faulty test response but a respective chain pattern bypassing the decompressor and the compactor does not produce a faulty test response.

15. The method of claim 12, further comprising, if the fault is determined to exist in the scan chains of the circuit-under-test, identifying a faulty scan chain in the circuit-under-test and a fault type based at least in part on the test responses to the chain patterns.

16. The method of claim 15, wherein one or more of the test responses to the chain patterns are compressed test responses output from the compactor, and wherein the act of identifying the faulty scan chain comprises applying a mathematical function representative of the compactor to the one or more of the test responses that are compressed test responses.

17. The method of claim 15, further comprising:

testing the circuit-under-test using multiple scan patterns; and

identifying one or more faulty scan cell candidates in the faulty scan chain based at least in part on compressed test responses to the scan patterns.

18. The method of claim 17, wherein the act of identifying the one or more faulty scan cell candidates comprises:

simulating failures in possible faulty scan cell candidates; and

comparing simulation results to one or more of the compressed test responses to the scan patterns, the transformation function performed by the compactor being incorporated into the simulation.

19. One or more computer-readable media made according to a method, the method comprising:

testing scan chains of a circuit-under-test using multiple chain patterns, wherein the testing comprises,

applying at least one of the chain patterns to the scan chains through a decompressor and a compactor coupled to the scan chains, and

applying at least one of the chain patterns to the scan chains while bypassing the decompressor and the compactor;

determining whether a fault exists in the scan chains of the circuit-under-test or in the decompressor or the compactor based at least in part on test responses to the chain patterns applied during the testing;

if the fault is determined to exist in the scan chains of the circuit-under-test, identifying a faulty scan chain in the circuit-under-test and a fault type based at least in part on the test responses to the chain patterns;

testing the circuit-under-test using multiple scan patterns;

identifying one or more faulty scan cell candidates in the faulty scan chain based at least in part on compressed test responses to the scan patterns; and

storing on the one or more computer-readable media a list of the identified one or more faulty scan cell candidates.

20. A computer-implemented method of testing an integrated circuit, comprising:

simulating one or more test patterns being applied to an integrated circuit design having scan chains and a compactor and thereby generating one or more expected compressed test responses, the act of simulating comprising modifying test values of the test patterns so that scan cells of a selected scan chain are loaded with either unknown values or a fixed value, the act of simulating further comprising using a transformation function representative of the compactor to generate the expected compressed test responses;

comparing the expected compressed test responses to observed compressed test responses obtained from testing a physical embodiment of the integrated circuit design with the one or more test patterns; and

determining a range of suspect scan cells in the selected scan chain based at least in part on the comparison.

21. The method of claim 20, wherein the test values are modified so that all scan cells of the selected scan chain are loaded with either the unknown values or the fixed value.

22. The method of claim 20, wherein the one or more test patterns comprise a first set of test patterns and wherein the one or more expected compressed test responses comprise a first set of expected compressed test responses, the method further comprising:

simulating a second set of one or more test patterns being applied to the integrated circuit design and thereby generating a second set of expected compressed test responses, the act of simulating the second set comprising,

modifying test values of the second set of test patterns so that at least some of the scan cells of the selected scan chain located before the last scan cell in the range are loaded with either unknown values or the fixed value, and so that at least some of the scan cells of the selected scan chain located after the last scan cell in the range are loaded with regular unmodified test values.

23. The method of claim 22, wherein the test values of the second set are modified so that all scan cells of the selected scan chain located before the last scan cell in the range are loaded with the unknown values or the fixed value.

24. The method of claim 22, wherein the first set of test patterns and the second set of test patterns are the same before modification.

25. The method of claim 22, wherein the range of suspect scan cells is a first range of suspect scan cells, the method further comprising:

comparing the second set of expected compressed test responses to the observed compressed test responses; and

determining a second range of suspect scan cells in the selected scan chain based at least in part on the comparison, the second range having fewer suspect scan cells than the first range.

26. The method of claim 20, reporting the range of suspect scan cells if the number of scan cells in the range is less than a predetermined number.

27. The method of claim 20, wherein the transformation function is a mathematical representation of the compactor that is applied to simulated uncompressed test responses.

28. The method of claim 20, wherein the transformation function is embedded into a representation of the integrated circuit design used during the simulation.

29. One or more computer-readable media made according to a method, the method comprising:

simulating one or more test patterns being applied to an integrated circuit design having scan chains and a compactor and thereby generating one or more expected compressed test responses, the act of simulating comprising modifying test values of the test patterns so that scan cells of a selected scan chain are loaded with either unknown values or a fixed value, the act of simulating further comprising using a transformation function representative of the compactor to generate the expected compressed test responses;

comparing the expected compressed test responses to observed compressed test responses obtained from testing a physical embodiment of the integrated circuit design with the one or more test patterns;

determining a range of suspect scan cells in the selected scan chain based at least in part on the comparison; and

storing in the one or more computer-readable media the determined range of suspect scan cells.

30. A computer-implemented method, comprising:

receiving a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test;

determining a transformation function performed by the compactor to the test responses captured in the circuit-under-test; and

diagnosing scan chain faults in one or more scan chains of the circuit-under-test using a diagnostic procedure that incorporates the transformation function.

31. The method of claim 30, wherein the diagnostic procedure comprises:

simulating one or more possible scan chain faults in the circuit-under-test to produce uncompressed faulty test responses; and

applying the transformation function to the uncompressed faulty test responses to determine compressed faulty test responses.

32. The method of claim 30, wherein the diagnostic procedure comprises:

modifying the circuit description to embed the transformation function upstream of scan cells in the circuit-under-test; and

simulating one or more possible scan chain faults using the modified circuit description.

33. The method of claim 30 performed during production testing of the circuit-under-test.

34. One or more computer-readable media made according to a method, the method comprising:

receiving a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in the circuit-under-test;

determining a transformation function performed by the compactor to the test responses captured in the circuit-under-test;

diagnosing scan chain faults in one or more scan chains of the circuit-under-test using a diagnostic procedure that incorporates the transformation function; and

storing in the one or more computer-readable media a list of the diagnosed scan chain faults.