Pipelined instruction processor with data bypassing and disabling circuit

• US 7,730,284 B2
• Filed: 03/17/2004
• Issued: 06/01/2010
• Est. Priority Date: 03/19/2003
• Status: Active Grant

• Current Assignee: Network System Technologies LLC
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Sethuraman, Ramanathan, Srinivasan, Balakrishnan, Alba Pinto, Carlos Antonio
• Primary Examiner(s): Li, Aimee J
• Application Number:
  US10/549,368
• Publication Number:
  US 20060212686A1
• Time in Patent Office: 2,267 Days
• Field of Search: 712/220, 712/218
• US Class Current: 712/218
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification
• CPC Class Codes: G06F 9/3865 using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to selectively disable storing of the results in the register file under control of the instructions.

Claims

1. An instruction processing device comprising:

an instruction issue unit for issuing successive instructions;

a plurality of pipe-line stages coupled to the instruction issue unit, at least one of the pipe-line stages comprising a functional unit for executing a command from the instructions;

a first register unit including a plurality of registers coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data, through a selector, to a circuit in a pipe-line stage preceding the first one of the pipeline stages;

a second register unit, coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit;

a disable circuit coupled to selectively disable storing of results in the second register unit under control of the instructions, wherein the result is passed to the functional unit via a bypass path before the storing of the result in the second register unit;

a multiplexer having inputs connected to an output of the selector and a read port of the second register unit; and

a bypass control unit arranged to compare a result register address for the result from a first one of the commands with an operand register address from a second one of the commands that follows the first one of the commands directly or indirectly, and to substitute a result from a selected register of the plurality of registers of the first register unit that contains the result for an operand from the second register unit in case of a match of the addresses;

wherein the bypass control unit is further arranged to control the selector and the multiplexer to select the result from the selected register for feeding back the result to the functional unit through the selector and the multiplexer.

2. The instruction processing device according to claim 1, wherein the second register unit comprise a plurality of registers, and wherein the first register unit contains fewer registers than the second register unit.

3. The instruction processing device according to claim 1, further comprising a plurality of functional units, arranged to execute respective commands from an instruction in parallel, the second register unit having a plurality of write ports for writing the result from respective ones of the functional unit, the disable circuit being arranged to disable writing at selected write ports, selected under control of the instructions.

4. The instruction processing device according to claim 1, wherein the first register unit comprises a chain of registers for supplying bypass operand data, arranged as a shift register with an input coupled to a result output of the first one of the stages and operative to shift the result through successive shift register stages in successive instruction cycles, at least if storing of the result in the second register unit is disabled, the chain extending further than necessary for writing the result into the second register unit.

5. The instruction processing device according to claim 4, wherein the registers in the chain are addressable from the commands.

6. The instruction processing device of claim 1, wherein the disable circuit is arranged to suppress a supply of clock signals to circuitry for writing the result into a register of the second register unit from a write port of the second register unit.

7. A method of executing a program of instructions in an instruction processor, the method comprising the acts of:

pipelining execution of commands from the instructions;

storing results of the commands in a first register unit including a plurality of registers;

passing results of executions by an execution unit back to the execution unit via a bypass path before storing of the results in a register file, wherein the bypass path includes a selector for selectively connecting a result of a selected register of the plurality of registers back to the execution unit through a multiplexer;

selectively using the result from the selected register bypassed from a pipelining stage as a bypassed operand instead of at least one of operands from the register file;

controlling the selector and the multiplexer to select the result from the selected register for feeding back the result to the functional unit through the selector and the multiplexer while selectively suppressing, under program control, writing of the first one of the results to the register file.

8. The method according to claim 7, comprising writing the result from the selected register into an addressable one of a plurality of bypass registers that are located to receive the result earlier during pipelining than the register file.

9. A computer readable medium embodying a computer program product comprising instructions for an instruction processor for implementing the method according to claim 7.

10. A method of compiling a program of instructions for an instruction processor, the method comprising the acts of:

generating a series of instructions;

first detecting for a result to be produced by a first one of the instructions which second one of the instructions use the result as operand;

second detecting whether it can be guaranteed that it will be possible to bypass the result in the instruction processor as operand for all second ones of the instructions without retrieving the result from a register file;

before storing of the result in the register file, passing the result to an execution unit, for executing a command from the instructions through a selector and a multiplexer;

generating information in the instruction to disable writing to the register file when it can be guaranteed that it will be possible to bypass the result as operand in the instruction processor for all second ones of the instructions while controlling the selector and the multiplexer to pass the result to the execution unit.

11. The method of compiling according to claim 10, comprising including an indication in the instructions that the result should be stored in one of a plurality of bypass registers that is addressable on writing and/or reading of the result to the plurality of bypass registers.

12. A computer readable medium embodying a computer program product comprising instructions for an instruction processor for implementing the method according to claim 10.