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Pipelined instruction processor with data bypassing and disabling circuit

  • US 7,730,284 B2
  • Filed: 03/17/2004
  • Issued: 06/01/2010
  • Est. Priority Date: 03/19/2003
  • Status: Active Grant
First Claim
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1. An instruction processing device comprising:

  • an instruction issue unit for issuing successive instructions;

    a plurality of pipe-line stages coupled to the instruction issue unit, at least one of the pipe-line stages comprising a functional unit for executing a command from the instructions;

    a first register unit including a plurality of registers coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data, through a selector, to a circuit in a pipe-line stage preceding the first one of the pipeline stages;

    a second register unit, coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit;

    a disable circuit coupled to selectively disable storing of results in the second register unit under control of the instructions, wherein the result is passed to the functional unit via a bypass path before the storing of the result in the second register unit;

    a multiplexer having inputs connected to an output of the selector and a read port of the second register unit; and

    a bypass control unit arranged to compare a result register address for the result from a first one of the commands with an operand register address from a second one of the commands that follows the first one of the commands directly or indirectly, and to substitute a result from a selected register of the plurality of registers of the first register unit that contains the result for an operand from the second register unit in case of a match of the addresses;

    wherein the bypass control unit is further arranged to control the selector and the multiplexer to select the result from the selected register for feeding back the result to the functional unit through the selector and the multiplexer.

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