System and method for saving and restoring a processor state without executing any instructions from a first instruction set

• US 7,730,330 B1
• Filed: 08/10/2005
• Issued: 06/01/2010
• Est. Priority Date: 06/16/2000
• Status: Expired due to Fees

• Current Assignee: Complex Memory LLC (IPValuation Partners, LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Anvin, H. Peter, Fleischmann, Marc
• Primary Examiner(s): CONNOLLY, MARK A
• Application Number:
  US11/201,624
• Time in Patent Office: 1,756 Days
• Field of Search: 713/320, 713/322, 713/324, 712/228, 365/228, 365/229
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3246 by software initiated power-off
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program execution at the instruction of the program that was asserted for execution when the CPU was powered down. The CPU is permitted to power down frequently, even during execution of a program, and results in reduced average overall power consumption.

Claims

1. A method of operating a processor having one or more registers and running a program comprising a first instruction and a next instruction from a first instruction set, said method comprising:

executing said first instruction;

in response to said executing, (i) saving the register context of said registers without executing any instructions from said first instruction set; and

(ii) removing power from said processor after said saving;

returning power to said processor after said removing;

after said returning, restoring said saved register context without executing any instructions from said first instruction set; and

resuming said running of said program with said next instruction.

2. The method of claim 1 wherein said saving is performed by an instruction sequence chosen from a second instruction set.

3. The method of claim 2 wherein said restoring is performed by a second instruction sequence chosen from said second instruction set.

4. The method of claim 3 wherein said first instruction set comprises an x86 instruction set.

5. The method of claim 1 wherein said program accesses a first memory and said saving accesses a second memory not accessible by said program.

6. The method of claim 1 wherein said second memory is powered independently of said processor.

7. The method of claim 1 further comprising setting a flag in response to said removing power.

8. The method of claim 1 further comprising:

intercepting a command to shut down the clock input to said processor; and

in response to said command, disabling said clock input and removing said power from said processor.

9. The method of claim 1 where said removing power comprises removing sufficient power to lose said register context.

10. The method of claim 9 wherein said step of removing sufficient power comprises removing all power.

11. The method of claim 1 wherein said saving comprises storing said register context in a memory.

12. The method of claim 11 wherein said memory and said registers retain state independently of each other.

13. The method of claim 11 wherein said memory is powered independently of said processor.

14. The method of claim 11 wherein said memory and said registers are in separate power domains.

15. The method of claim 11 wherein said memory is not addressable by said first instruction set.

16. The method of claim 11 wherein said memory is not accessible by any instruction from said first instruction set.

17. The method of claim 11 wherein said memory is not visible to any instruction from said first instruction set.

18. The method of claim 11 wherein said memory is private with respect to said first instruction set.

19. The method of claim 11 wherein said memory is internal to said processor.

20. The method of claim 19 wherein said processor is on an integrated circuit and said memory is on said integrated circuit.

21. The method of claim 11 wherein said memory is external to said processor.

22. The method of claim 1 wherein said first instruction set comprises an x86 instruction set.

23. The method of claim 1 wherein instructions from said first instruction set may be executed in a plurality of modes.

24. The method of claim 23 wherein said plurality of modes comprises a real mode and a protected mode.

25. The method of claim 23 wherein said plurality of modes comprises a privileged mode and a non-privileged mode.

26. The method of claim 23 wherein said first instruction set comprises an x86 instruction set and said plurality of modes comprises a real mode, a protected mode and a system management mode.

27. The method of claim 1 wherein said processor has additional context, and said method further comprises:

before said removing power, saving at least a portion of said additional context without executing any additional instructions from said first instruction set; and

after said returning power, restoring said saved portion without executing any additional instructions from said first instruction set.

28. The method of claim 27 wherein said portion is in system component registers.

29. The method of claim 28 wherein said system component registers comprise Northbridge registers.

30. The method of claim 27 wherein said portion is in a cache.

31. The method of claim 27 wherein said portion comprises at least a part of the internal state of said processor.

32. The method of claim 1 wherein said saving comprises executing microcode.

33. The method of claim 1 wherein said running comprises interpreting instructions from said first instruction set.

34. The method of claim 33 wherein said running comprises translating instructions from said first instruction set.

35. A computer system comprising:

a central processing unit (CPU) comprising a first memory accessible only to said CPU; and

a second memory coupled to said CPU, said memory unit containing instructions that when executed implement a computer-implemented method of operating said processor, said method comprising;

executing a first instruction of a first instruction set of a program to place said processor into a state;

saving said state without executing any instructions from said first instruction set;

removing power from said processor after said saving;

returning power to said processor after said removing;

after said returning, restoring said state without executing any instructions from said first instruction set; and

resuming said running of said program with a next instruction of said first instruction set.

36. The computer system of claim 35 wherein said saving is performed by an instruction sequence chosen from a second instruction set.

37. The computer system of claim 36 wherein said restoring is performed by a second instruction sequence chosen from said second instruction set.

38. The computer system of claim 37 wherein said first instruction set comprises an x86 instruction set.

39. The computer system of claim 35 wherein said program accesses a first memory and said saving accesses a second memory not accessible by said program.

40. The computer system of claim 35 wherein said second memory is powered independently of said processor.

41. The computer system of claim 35 wherein said method further comprises setting a flag in response to said removing power.

42. A computer-readable medium embodying instructions that cause a computer to perform a method of operating a processor running a program comprising a first instruction and a next instruction from a first instruction set, said method comprising:

executing said first instruction to place said processor into a state;

saving said state without executing any instructions from said first instruction set;

removing power from said processor after said saving;

returning power to said processor after said removing;

after said returning, restoring said state without executing any instructions from said first instruction set; and

resuming said running of said program with said next instruction.

43. The computer-readable medium of claim 42 wherein said saving is performed by an instruction sequence chosen from a second instruction set.

44. The computer-readable medium of claim 43 wherein said restoring is performed by a second instruction sequence chosen from said second instruction set.

45. The computer-readable medium of claim 44 wherein said first instruction set comprises an x86 instruction set.

46. The computer-readable medium of claim 42 wherein said program accesses a first memory and said saving accesses a second memory not accessible by said program.

47. A method of operating a CPU including one or more registers and running a program comprising a first instruction from a first instruction set, said method comprising:

executing said first instruction;

in response to said executing, (i) saving the state of said registers without executing any additional instructions from said first instruction set; and

(ii) initiating an action that may cause the state of said registers to become undefined; and

restoring said saved state of said registers without executing any additional instructions from said first instruction set.

48. The method of claim 47 wherein said CPU has additional context, and said method further comprises:

in response to said executing, saving at least a portion of said additional context without executing any additional instructions from said first instruction set; and

restoring said saved portion without executing any additional instructions from said first instruction set.

49. The method of claim 48 wherein said portion is in system component registers.

50. The method of claim 49 wherein said system component registers comprise Northbridge registers.

51. The method of claim 48 wherein said portion is in a cache.

52. The method of claim 48 wherein said portion comprises at least a part of the internal state of said CPU.

53. The method of claim 48 wherein said portion comprises a register context.

54. The method of claim 47 wherein said action comprises powering down said CPU.

55. The method of claim 47 wherein said action comprises removing sufficient power from said CPU such that said state may become undefined.

56. The method of claim 55 wherein said step of removing sufficient power comprises removing all power.

57. The method of claim 47 wherein said action comprises turning off power to said CPU.

58. The method of claim 47 wherein said program has a second instruction from said first instruction set, said method comprising:

after said restoring, continuing said running of said program with said second instruction wherein said second instruction programmatically follows said first instruction.

59. The method of claim 47 wherein said program has a second instruction from said first instruction set, said method comprising:

after said restoring, continuing said running of said program with said second instruction wherein said second instruction is the next instruction of said program after said first instruction.

60. The method of claim 47 wherein said saving comprises storing said state in a memory.

61. The method of claim 60 wherein said memory and said registers retain state independently of each other.

62. The method of claim 60 wherein said memory is powered independently of said registers.

63. The method of claim 60 wherein said memory and said registers are in separate power domains.

64. The method of claim 60 wherein said memory is not addressable by said first instruction set.

65. The method of claim 60 wherein said memory is not accessible by any instruction from said first instruction set.

66. The method of claim 60 wherein said memory is not visible to any instruction from said first instruction set.

67. The method of claim 60 wherein said memory is private with respect to said first instruction set.

68. The method of claim 60 wherein said memory is internal to said CPU.

69. The method of claim 68 wherein said CPU is on an integrated circuit and said memory is on said integrated circuit.

70. The method of claim 60 wherein said memory is external to said CPU.

71. The method of claim 47 wherein said first instruction set is an x86 instruction set.

72. The method of claim 47 wherein instructions from said first instruction set may be executed in a plurality of modes.

73. The method of claim 72 wherein said plurality of modes comprises a real mode and a protected mode.

74. The method of claim 72 wherein said first instruction set comprises an x86 instruction set and said plurality of modes comprises a real mode, a protected mode and a system management mode.

75. The method of claim 72 wherein said plurality of modes comprises a privileged mode and a non-privileged mode.

76. The method of claim 47 wherein said saving comprises executing instructions from a second instruction set.

77. The method of claim 47 wherein said saving comprises executing microcode.

78. The method of claim 47 wherein said running comprises interpreting instructions from said first instruction set.

79. The method of claim 78 wherein said running comprising translating instructions from said first instruction set.

80. The method of claim 47 wherein said saving comprises interpreting said first instruction.

81. The method of claim 47 wherein said restoring comprises executing instructions from a second instruction set.

82. The method of claim 47 wherein said restoring comprises executing microcode.

83. The method of claim 47 wherein said saving comprises setting a flag and said restoring comprises checking said flag.

84. The method of claim 83 wherein said flag comprises a signature.

85. A method of operating a CPU including one or more registers and running a program comprising a first instruction from a first instruction set, said method comprising:

executing said first instruction;

in response to said executing, saving the state of said registers without executing any additional instructions from said first instruction set; and

restoring said saved state of said registers without executing any additional instructions from said first instruction set if power to the CPU has been lost.

86. The method of claim 85 wherein said CPU has additional context, and said method further comprises:

in response to said executing, saving at least a portion of said additional context in a memory without executing any additional instructions from said first instruction set; and

restoring said saved portion without executing any additional instructions from said first instruction set.

87. The method of claim 86 wherein said portion is in system component registers.

88. The method of claim 87 wherein said system component registers comprise Northbridge registers.

89. The method of claim 86 wherein said portion is in a cache.

90. The method of claim 86 wherein said portion comprises at least a part of the internal state of said CPU.

91. A method of operating a CPU including one or more registers and running a program comprising a first instruction from a first instruction set, said method comprising:

executing said first instruction;

in response to said executing, (i) saving the state of said registers without executing any additional instructions from said first instruction set; and

(ii) stopping further execution of instructions; and

restoring said state of said registers without executing any additional instructions from said first instruction set.

92. The method of claim 91 wherein said CPU has additional context, and said method further comprises:

in response to said executing, saving at least a portion of said additional context in a memory without executing any additional instructions from said first instruction set; and

restoring said saved portion without executing any additional instructions from said first instruction set.

93. The method of claim 92 wherein said portion is in system component registers.

94. The method of claim 93 wherein said system component registers comprise Northbridge registers.

95. The method of claim 92 wherein said portion is in a cache.

96. The method of claim 92 wherein said portion comprises at least a part of the internal state of said CPU.

97. A method of operating a processor and one or more system components, said processor having registers and running a program comprising a first instruction from a first instruction set, said method comprising:

executing said first instruction;

in response to said executing, (i) saving the states of said registers and said system components, without executing any additional instructions from said first instruction set; and

(ii) initiating an action that may cause the state of said registers or the state of said system components to become undefined; and

restoring said saved state of said registers and said system components without executing any additional instructions from said first instruction set.

98. The method of claim 97 wherein said processor is on an integrated circuit and said system components are on said integrated circuit.

99. The method of claim 97 wherein said system components comprise a Northbridge.

100. The method of claim 97 wherein said CPU has additional context, and said method further comprises:

in response to said executing, saving at least a portion of said additional context in a memory without executing any additional instructions from said first instruction set; and

restoring said saved portion without executing any additional instructions from said first instruction set.

101. The method of claim 100 wherein said portion is in a cache.

102. The method of claim 100 wherein said portion comprises at least a part of the internal state of said CPU.

103. A CPU for executing instructions from a first instruction set, said CPU comprising:

one or more registers holding a state;

wherein

said CPU is adapted, upon executing a first instruction from said first instruction set, (i) to save said state in a memory without executing any additional instructions from said first instruction set; and

(ii) to initiate an action that may cause the state of said registers to become undefined; and

said CPU is adapted, in response to an event, to restore the saved state of said registers from said memory without executing any additional instructions from said first instruction set.

104. The CPU of claim 103, wherein said CPU is further adapted, after restoring said state, to execute a second instruction from said first instruction set where said second instruction programmatically follows said first instruction.

105. The CPU of claim 103, wherein said CPU is further adapted, after restoring said state, to execute a second instruction where said second instruction is the next instruction in said first instruction set to be executed after said first instruction.

106. The CPU of claim 103 wherein said action comprises powering down said CPU.

107. The CPU of claim 103 wherein said action comprises removing sufficient power from said CPU such that said state may become undefined.

108. The CPU of claim 107 wherein said removing sufficient power comprises removing all power.

109. The CPU of claim 103 wherein said action comprises turning off power to said CPU.

110. The CPU of claim 103 wherein said event comprises detection of activity.

111. The CPU of claim 103 wherein said event comprises restoration of power to said CPU.

112. The CPU of claim 111 wherein said restoration of power comprises restoration of full power.

113. The CPU of claim 103 wherein said memory is not visible to instructions from said first instruction set.

114. The CPU of claim 103 wherein said memory is not addressable by said first instruction set.

115. The CPU of claim 103 wherein said memory is not accessible by instructions from said first instruction set.

116. The CPU of claim 103 wherein said memory is private with respect to said first instruction set.

117. The CPU of claim 103 wherein said memory and said registers retain state independently of each other.

118. The CPU of claim 103 wherein said memory is powered independently of said registers.

119. The CPU of claim 103 wherein said memory and said registers are in separate power domains.

120. The CPU of claim 103 wherein said memory is internal to said CPU.

121. The CPU of claim 120 wherein said CPU is on an integrated circuit and said memory is on said integrated circuit.

122. The CPU of claim 103 wherein said memory is external to said CPU.

123. The CPU of claim 103 wherein said first instruction set is an x86 instruction set.

124. The CPU of claim 103 wherein instructions from said first instruction set may be executed in a plurality of modes.

125. The CPU of claim 124 wherein said plurality of modes comprises a real mode and a protected mode.

126. The CPU of claim 124 wherein said first instruction set comprises an x86 instruction set and said plurality of modes comprises a real mode, a protected mode and a system management mode.

127. The CPU of claim 124 wherein said plurality of modes comprises a privileged mode and a non-privileged mode.

128. The CPU of claim 103 wherein said adaptation to save comprises an adaptation to execute instructions from a second instruction set.

129. The CPU of claim 103 wherein said adaptation to save comprises an adaptation to execute microcode.

130. The CPU of claim 103 wherein said CPU is adapted to interpret instructions from said first instruction set.

131. The CPU of claim 130 wherein said CPU is adapted to translate instructions from said first instruction set.

132. The CPU of claim 103 wherein said adaptation to save comprises interpreting said first instruction.

133. The CPU of claim 103 wherein said adaptation to restore comprises an adaptation to execute instructions from a second instruction set.

134. The CPU of claim 103 wherein said adaptation to restore comprises an adaptation to execute microcode.

135. The CPU of claim 103, further comprising:

a flag;

wherein said adaptation to save further comprises an adaptation to set said flag; and

said adaptation to restore comprises checking said flag.

136. The CPU of claim 135 wherein said flag comprises a signature.

137. The CPU of claim 103 wherein CPU has additional context, and said CPU further comprises:

said executing adaptation is further adapted to save at least a portion of said additional context without executing any additional instructions from said first instruction set; and

said CPU is adapted, in response to said event to restore said saved portion without executing any additional instructions from said first instruction set.

138. The CPU of claim 137 wherein said portion is in system component registers.

139. The CPU of claim 138 wherein said system component registers comprise Northbridge registers.

140. The CPU of claim 137 wherein said portion is in a cache.

141. The CPU of claim 137 wherein said portion comprises at least a part of the internal state of said CPU.

142. A method of operating a CPU running a program comprising a first instruction from a first instruction set and having one or more registers holding program counter information, said method comprising:

executing said first instruction;

in response to said executing, (i) saving the program counter information without executing any additional instructions from said first instruction set; and

(ii) initiating an action that may cause said program counter information to become undefined; and

restoring said saved program counter information without executing any additional instructions from said first instruction set.

143. The method of claim 142 wherein said CPU has additional context, and said method further comprises:

in response to said executing, saving at least a portion of said additional context in a memory without executing any additional instructions from said first instruction set; and

restoring said saved portion without executing any additional instructions from said first instruction set.

144. The method of claim 143 wherein said portion is in additional CPU registers.

145. The method of claim 143 wherein said portion is in system component registers.

146. The method of claim 145 wherein said system component registers comprise Northbridge registers.

147. The method of claim 143 wherein said portion is in a cache.

148. The method of claim 143 wherein said portion comprises at least a part of the internal state of said CPU.

149. The method of claim 143 wherein said portion comprises a register context.

150. A CPU for executing instructions from a first instruction set, said CPU comprising:

one or more registers holding program counter information;

wherein

said CPU is adapted, upon executing a first instruction from said first instruction set, (i) to save the program counter information without executing any additional instructions from said first instruction set; and

(ii) to initiate an action that may cause said program counter information to become undefined; and

said CPU is adapted, in response to an event, to restore said saved program counter information without executing any additional instructions from said first instruction set.

151. The CPU of claim 150 wherein CPU has additional context, and said CPU further comprises:

said executing adaptation is further adapted to save at least a portion of said additional context without executing any additional instructions from said first instruction set; and

said CPU is adapted, in response to said event to restore said saved portion without executing any additional instructions from said first instruction set.

152. The CPU of claim 151 wherein said portion is in additional CPU registers.

153. The method of claim 151 wherein said portion is in system component registers.

154. The method of claim 153 wherein said system component registers comprise Northbridge registers.

155. The CPU of claim 151 wherein said portion is in a cache.

156. The CPU of claim 151 wherein said portion comprises at least a part of the internal state of said CPU.

157. The CPU of claim 151 wherein said portion comprises a register context.