Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits

• US 7,730,338 B2
• Filed: 04/29/2008
• Issued: 06/01/2010
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Wang, David T., Smith, Michael John Sebastian, Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US12/111,828
• Publication Number:
  US 20080239858A1
• Time in Patent Office: 763 Days
• Field of Search: 713/320, 713/323, 713/324, 713/300, 365/226, 365/227
• US Class Current: 713/320
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.

Claims

1. A sub-system, comprising:

an interface circuit in communication with a plurality of memory circuits and a system, the interface circuit operable to interface the plurality of memory circuits and the system for autonomously performing a first power management operation in a first command operation period on a first memory circuit of the plurality of memory circuits and a second power management operation in a second command operation period on a second memory circuit of the plurality of memory circuits.

2. The sub-system of claim 1, wherein the first power management operation is initiated by the interface circuit autonomously.

3. The sub-system of claim 1, wherein the power management operation is initiated by at least one non-power management signal.

4. The sub-system of claim 3, wherein the non-power management signal includes a control signal.

5. The sub-system of claim 4, wherein the control signal is selected from the group consisting of an address signal and a data signal.

6. The sub-system of claim 4, wherein the control signal is associated with an operation selected from the group consisting of an activate operation, a precharge operation, a write operation, a read operation, a mode register write operation, a mode register read operation, and a refresh operation.

7. The sub-system of claim 1, wherein the first power management operation is initiated in response to at least one non-power related state of one or more of the memory circuits.

8. The sub-system of claim 7, wherein the at least one state is selected from the group consisting of a predetermined combination of commands issued to the one or more of the memory circuits, a predetermined pattern of commands issued to the one or more of the memory circuits, and a predetermined absence of commands issued to the one or more of the memory circuits.

9. The sub-system of claim 1, wherein the power management operation includes a power saving operation.

10. The sub-system of claim 1, wherein the interface circuit is intelligent.

11. The sub-system of claim 1, wherein the interface circuit is selected from the group consisting of a buffer, a register, a memory controller, and an advanced memory buffer (AMB).

12. The sub-system of claim 1, wherein the interface circuit and the memory circuits take the form of a stack.

13. The sub-system of claim 12, wherein the stack includes a single interface circuit.

14. The sub-system of claim 12, wherein the stack includes a plurality of interface circuits.

17. The sub-system of claim 1, wherein the first command operation period is defined for a sequence, combination, or pattern of commands.

18. The sub-system of claim 1, wherein the second command operation period is defined for a sequence, combination, or pattern of commands.

19. The sub-system of claim 1, wherein the first and second command operation periods are not the same periods.

20. The sub-system of claim 1, wherein the first command within the first command operation period performed on the first memory circuit corresponds to a mapping of a plurality of physical DRAM circuits.

21. The sub-system of claim 1, wherein the interface circuit identifies at least one memory circuit that is not currently being accessed by the system.

22. The sub-system of claim 1, wherein the first power management operation includes placing at least one first memory circuit into a power down mode and the second power management operation includes bringing at least one second memory circuit out of power down mode.

23. The sub-system of claim 1, wherein identification of the first command operation period is based on commands directed to the first memory circuit.

24. The sub-system of claim 1, wherein the first power management operation is initiated in response to a predetermined combination of commands issued to the first memory circuit.

25. The sub-system of claim 1, wherein the first power management operation is initiated in response to a predetermined pattern of commands issued to the first memory circuit.

26. The sub-system of claim 1, wherein the first power management operation is initiated in response to predetermined absence of commands issued to the first memory circuit.

27. The sub-system of claim 1, wherein the at least one interface circuit comprises at least two interface circuits.

28. The sub-system of claim 27, wherein the least two interface circuits comprise a first interface circuit and a second interface circuit.

29. The sub-system of claim 28 wherein a first interface circuit introduces a first delay and a second interface circuit introduces a second delay.

15. A method, comprising:

interfacing a plurality of memory circuits and a system; and

autonomously performing a first power management operation in a first command operation period on a first memory circuit of the plurality of memory circuits and a second power management operation in a second command operation period on a second memory circuit of the plurality of memory circuits.

16. A system, comprising:

a plurality of memory circuits; and

an interface circuit in communication with the plurality of memory circuits and a system, the interface circuit operable to interface the plurality of memory circuits and the system for autonomously performing a first power management operation in a first command operation period on a first memory circuit of the plurality of memory circuits and a second power management operation in a second command operation period on a second memory circuit of the plurality of memory circuits.