Providing high availability in a PCI-Express™ link in the presence of lane faults

• US 7,730,376 B2
• Filed: 03/27/2008
• Issued: 06/01/2010
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Das Sharma, Debendra
• Primary Examiner(s): KERVEROS, DEMETRIOS C
• Application Number:
  US12/056,777
• Publication Number:
  US 20080178052A1
• Time in Patent Office: 796 Days
• Field of Search: 714/712, 714/724, 714/742
• US Class Current: 714/742
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06

Abstract

A method, device, and system are disclosed. In one embodiment, the method comprises discovering a failure on a PCI Express interconnect, determining whether a failure override bit has been set to override the standard PCI Express Polling. Compliance state for the failure on the PCI Express interconnect, and if the failure override bit has been set, entering PCI Express Polling. Configuration state if any one lane of the interconnect successfully completes the transmitting and receiving training sequence requirements in PCI Express Polling.Active state.

Claims

1. A device, comprising:

a plurality of transmitters, each of the plurality of transmitters to originate a transmission of information on a lane of a two-way differential serial link, comprising multiple lanes, during normal operation of the link;

a plurality of receivers, each of the plurality of receivers to receive information from a lane of the link during normal operation of the link;

a failure discovery unit to detect failures at any location on the link; and

a link training unit to cause at least one lane of the link to be brought into an active state to continue the transmission of information if at least one lane of the link is still operational after a failure detection on the link.

2. The device of claim 1, wherein each lane of the link comprises at least two wires to transmit information and at least two other wires to receive information.

3. The device of claim 2, wherein the device is further operable to:

detect a transmitter from a second device coupled to the link in at least one but not all lanes of the link; and

operate the link in a degraded mode without use of the one or more lanes with no detected transmitter.

4. The device of claim 3, wherein detecting a transmitter further comprises detecting an exit from an electrical idle state from the transmitter.

5. The device of claim 2, wherein the device is further operable to:

detect a receiver from a second device coupled to the link in at least one but not all lanes of the link; and

operate the link in a degraded mode without use of the one or more lanes with no detected receiver.

6. The device of claim 5, wherein the device is further operable to:

enter a configuration state upon discovery of the failure;

transmit a training sequence in every lane of the link that a receiver was detected while in the configuration state; and

transmit a test pattern in the one or more lanes of the link that did not detect a receiver while in the configuration state.

7. A system, comprising:

a two-way differential serial link, comprising multiple lanes;

a first device coupled to the link; and

a second device coupled to the link, the second device to

originate a transmission of information across the link to the first device;

detect a failure at any location on the link; and

cause at least one lane of the link to be brought into an active state to continue the transmission of information if at least one lane of the link is still operational after a failure detection on the link;

wherein the first device and second device each including a transmitter and receiver to transmit and receive information on each lane of the link during normal operation of the link, wherein each lane of the link comprises at least two wires to transmit information and at least two other wires to receive information.

8. The system of claim 7, wherein the second device is further operable to:

detect a transmitter from the first device in at least one but not all lanes of the link; and

operate the link in a degraded mode without use of the one or more lanes with no detected transmitter.

9. The system of claim 8, wherein detecting a transmitter further comprises detecting an exit from an electrical idle state from the transmitter.

10. The system of claim 7, wherein the second device is further operable to:

detect a receiver from a first device in at least one but not all lanes of the link; and

operate the link in a degraded mode without use of the one or more lanes with no detected receiver.

11. The system of claim 10, wherein the second device is further operable to:

enter a configuration state upon discovery of the failure;

transmit a training sequence in every lane of the link that a receiver was detected while in the configuration state; and

transmit a test pattern in the one or more lanes of the link that did not detect a receiver while in the configuration state.

12. The system of claim 7, wherein the second device further comprises:

a configuration register including a link failure override bit, the second device to cause the at least one lane of the link to be brought into an active state to continue the transmission of information when the link failure override bit has been set.

13. A method, comprising:

discovering a failure at any location on a two-way differential serial links, comprising multiple lanes, wherein the link transmits and receives data on each lane when a failure has not been detected; and

causing at least one lane of the link to be brought into an active state to allow the transmission of information if at least one lane of the link is still operational after a failure detection on the link.

14. The method of claim 13, wherein the link couples a first device and a second device together to allow the transmission of information to originate from the first device targeting the second device and to originate from the second device targeting the first device.

15. The method of claim 14, wherein the first device and second device each including a transmitter and receiver to transmit and receive information on each lane of the link, and wherein each lane of the link comprises at least two wires to transmit information and at least two other wires to receive information.

16. The method of claim 15, further comprising:

detecting a transmitter from the first device in at least one but not all lanes of the link; and

operating the link in a degraded mode without use of the one or more lanes with no detected transmitter.

17. The method of claim 15, further comprising:

detecting a receiver from the first device in at least one but not all lanes of the link; and

operating the link in a degraded mode without use of the one or more lanes with no detected receiver.

18. The method of claim 17, further comprising:

entering a configuration state when the link failure is discovered; and

transmitting a training sequence in every lane of the link that a receiver was detected while in the configuration state; and

transmitting a test pattern in the one or more lanes of the link that did not detect a receiver while in the configuration state.

19. The method of claim 17, further comprising:

entering a configuration state when the link failure is discovered; and

transmitting a training sequence of information across all lanes of the link upon entering the configuration state.