Test access control for secure integrated circuits

• US 7,730,545 B2
• Filed: 05/23/2005
• Issued: 06/01/2010
• Est. Priority Date: 05/23/2005
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Milne, George James, Swaine, Andrew Brookfield, Felton, Donald
• Primary Examiner(s): Hoffman; Brandon S
• Application Number:
  US11/134,514
• Publication Number:
  US 20060282734A1
• Time in Patent Office: 1,835 Days
• Field of Search: None
• US Class Current: 726/27
• CPC Class Codes: G01R 31/31719 Security aspects, e.g. preventing unauthorised access during test
• CPC Class Codes: G06F 21/35 communicating wirelessly

Abstract

Test access to an integrated circuit 2 is controlled by the use of test access enabling keys. A plurality of different test access enabling levels may be supported corresponding to different keys. The test access control may be performed by dedicated hardware or software executing a secure privilege mode.

Claims

1. An integrated circuit comprising:

a test circuit configured to perform test operations upon at least a portion of said integrated circuit; and

a test rights controller configured to receive and authenticate a test access request;

wherein

if a received test access request passes authentication by said test rights controller, then said test rights controller is configured to permit said test circuit to perform a level of test operations corresponding to said received test access request; and

if said received test access request does not pass authentication by said test rights controller, then said test rights controller is operable to prevent said test circuit performing test operations, wherein said test access request includes a test rights enabling key and said test rights controller comprises;

an interface circuit configured to read said test rights enabling key from an external data storage device; and

a key authenticator configured to authenticate said test rights enabling key read from said external data storage device.

2. An integrated circuit as claimed in claim 1, wherein if said test access request is received from a trusted source, then said test rights controller permits said test circuit to perform said level of test operations.

3. An integrated circuit as claimed in claim 1, wherein said key authenticator is a software controlled processor configured to compare said test rights enabling key with one or more predetermined authentic test rights enabling keys stored within said test rights controller.

4. An integrated circuit as claimed in claim 1, wherein said external data storage device is one of:

a subscriber identification module;

a smart card; and

a memory card.

5. An integrated circuit as claimed in claim 1, wherein said test rights controller is configured to receive said test rights enabling key via a test data channel.

6. An integrated circuit as claimed in claim 5, wherein said test data channel is a serial scan chain.

7. An integrated circuit as claimed in claim 1, wherein said test circuit is configured to provide a plurality of levels of tests operations.

8. An integrated circuit as claimed in claim 7, wherein said plurality of levels include:

a level enabling test operations which non-intrusively trace data processing operations within said integrated circuit; and

a level enabling test operations which interrupt data processing operations within said integrated circuit.

9. An integrated circuit as claimed in claim 7, wherein said plurality of levels include different levels correspond to permitting or not permitting test operations during associated modes of operation of a software controlled processor within said integrated circuit.

10. An integrated circuit as claimed in claim 7, wherein said plurality of levels include different levels correspond to permitting or not permitting test operations to be performed upon different portions of a system-on-chip integrated circuit.

11. An integrated circuit as claimed in claim 1, wherein said test operations include one or more of:

capture of data values from said integrated circuit;

writing of data values to said integrated circuit;

setting breakpoints in programs executing on said integrated circuit; and

setting watchpoints for data values accessed by said integrated circuit.

12. An integrated circuit as claimed in claim 1, wherein said test circuit includes one or more of:

serial scan chains; and

a trace data capture circuit.

13. An integrated circuit comprising:

test circuit means for performing test operations upon at least a portion of said integrated circuit; and

test rights controller means for receiving and authenticating a test access request;

wherein

if a received test access request passes authentication by said test rights controller means, then said test controller means is configured to permit said test circuit to perform a level of test operations corresponding to said received test access request; and

if said received test access request does not pass authentication by said test rights controller, then said test rights controller means is configured to prevent said test circuit means performing test operations, wherein said test access request includes a test rights enabling key and said test rights controller means comprises;

an interface circuit means for reading said test rights enabling key from an external data storage device; and

a key authentication means for authenticating said test rights enabling key read from said external data storage device.

14. A method controlling test access to an integrated circuit comprising:

providing a test circuit configured to perform test operations upon at least a portion of said integrated circuit; and

receiving and authenticating a test access request with a test right controller;

wherein if a received test access request passes authentication, then said test circuit is permitted to perform a level of test operations corresponding to said received test access request; and

if said received test rights access request does not pass authentication, then said test circuit is not permitted to perform test operations, wherein said test access request includes a test rights enabling key and said test rights controller comprises;

an interface circuit configured to read said test rights enabling key from an external data storage device; and

a key authenticator configured to authenticate said test rights enabling key read from said external data storage device.

15. A method as claimed in claim 14, wherein if said test access request is received from a trusted source, then said test rights controller permits said test circuit to perform said level of test operations.

16. A method as claimed in claim 14, wherein said key authenticator is a software controlled processor is operable to compare said test rights enabling key with one or more predetermined authentic test rights enabling keys stored within said test rights controller.

17. A method as claimed in claim 14, wherein said external data storage device is one of:

a subscriber identification module;

a smart card; and

a memory card.

18. A method as claimed in claim 14, wherein said test rights controller is configured to receive said test rights enabling key via a test data channel.

19. A method as claimed in claim 18, wherein said test data channel is a serial scan chain.

20. A method as claimed in claim 14, wherein said test circuit is configured to provide a plurality of levels of tests operations.

21. A method as claimed in claim 20, wherein said plurality of levels include:

a level enabling test operations which non-intrusively trace data processing operations within said integrated circuit; and

a level enabling test operations which interrupt data processing operations within said integrated circuit.

22. A method as claimed in claim 20, wherein said plurality of levels include different levels correspond to permitting or not permitting test operations during associated modes of operation of a software controlled processor within said integrated circuit.

23. A method as claimed in claim 20, wherein said plurality of levels include different levels correspond to permitting or not permitting test operations to be performed upon different portions of a system-on-chip integrated circuit.

24. A method as claimed in claim 14, wherein said test operations include one or more of

capture of data values from said integrated circuit;

writing of data values to said integrated circuit;

setting breakpoints in programs executing on said integrated circuit; and

setting watchpoints for data values accessed by said integrated circuit.

25. A method as claimed in claim 14, wherein said test circuit includes one or more of:

serial scan chains; and

a trace data capture circuit.