Hybrid MRAM array structure and operation

• US 7,732,221 B2
• Filed: 05/18/2004
• Issued: 06/08/2010
• Est. Priority Date: 06/11/2002
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Hush, Glen, Seyyedy, Mirmajid
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): LULIS, MICHAEL P
• Application Number:
  US10/847,338
• Publication Number:
  US 20040213044A1
• Time in Patent Office: 2,212 Days
• Field of Search: 438/3, 438/128, 438/129, 438/241, 365/158, 365/171, 365/173, 365/203, 257/421, 257/E21.665, 257/E27.006
• US Class Current: 438/3
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2213/71 Three dimensional array

Abstract

This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Claims

1. A method of fabricating a memory device, comprising:

providing a substrate;

forming an access transistor on said substrate, said access transistor having a first active area and a second active area;

providing a bit line in electrical contact with said first active area;

providing an interconnect in electrical contact with said second active area;

forming a first write only line;

forming a first sense line associated with a first plurality of memory bits, said first sense line being formed over said access transistor and in electrical contact with said interconnect, wherein said interconnect is in electrical contact with said first plurality of memory bits via said first sense line;

forming said first plurality of memory bits, each of said first plurality of memory bits being formed over, and in electrical contact with, said first sense line;

forming a second sense line, said second sense line being formed over said first plurality of memory bits and in electrical contact with said interconnect;

forming a second plurality of memory bits, each of said second plurality of memory bits being formed over, and in electrical contact with, said second sense line.

2. The method of claim 1, wherein the act of forming said first plurality of memory bits comprises:

forming a plurality of first memory storage regions over said first sense line; and

forming a first plurality of common lines;

wherein each of said first plurality of common lines is formed over one of said plurality of first memory storage regions.

3. The method of claim 2, wherein said step of forming said first sense line comprises:

forming a first write only line;

forming a first dielectric line over said first write only line; and

forming said first sense line over said first write only line.

4. The method of claim 3, wherein

said step of forming said first sense line comprises:

forming a first write only line;

forming a first dielectric line over said first write only line; and

forming said first sense line over said first write only line; and

said step of forming said second sense line comprises;

forming a second write only line;

forming a second dielectric line over said second write only line; and

forming said second sense line over said second write only line; and

said step of forming said second plurality of memory bits comprises;

forming a plurality of second memory storage regions over said second sense line; and

forming a second plurality of common lines, wherein each of said second plurality of common lines being formed over one of said plurality of second memory storage regions.

5. The method of claim 2, wherein said step of forming said second plurality of memory bits comprises:

forming a plurality of second memory storage regions over said first sense line; and

forming a second plurality of common lines;

wherein each of said second plurality of common lines is formed over one of said plurality of second memory storage regions.

6. The method of claim 2, wherein each of said first plurality of common lines is formed orthogonal to said first sense line.

7. The method of claim 6, wherein

said step of forming said second plurality of memory bits comprises:

forming a plurality of second memory storage regions over said first sense line; and

forming a second plurality of common lines, each of said second plurality of common lines being formed over one of said plurality of second memory storage regions, and each of said second plurality of common lines being orthogonal to said second sense line.

8. The method of claim 1, further comprising:

providing a sense amplifier in electrical contact with said bit line.

9. The method of claim 1, wherein said step of forming said access transistor comprises:

forming a source region;

forming a drain region;

forming a gate structure between said source region and said drain region;

providing a plurality of conductive plugs to said source region and said drain region, said bit line being in electrical contact with one of said conductive plugs and said interconnect being in electrical contact with another of said conductive plugs.

10. The method of claim 1, wherein each of said first plurality of memory bits and each of said second plurality of memory bits is a magnetic memory element.

11. The method of claim 1, wherein each of said first plurality of memory bits and each of said second plurality of memory bits is a programmable conductor variable resistance memory element.

12. The method of claim 1, wherein each of said first plurality of memory bits and each of said second plurality of memory bits is a phase-changing chalcogenide memory element.

13. A method for forming a memory device, comprising:

providing a sense amplifier;

providing an interconnect;

providing an access transistor, said access transistor being capable of electrically connecting said sense amplifier with said interconnect;

providing a plurality of array planes over said access transistor, each of said array planes comprising a plurality of memory cells organized into a plurality of rows and a plurality of columns;

providing a plurality of common lines, each of said common lines being associated with and coupled to a respective column of said plurality of memory cells; and

forming a first write only line;

providing a plurality of sense lines, each of said sense lines being associated with and coupled to a respective row of said plurality of memory cells

wherein each of said common lines is coupled to one of said plurality of sense lines on each of said plurality of array planes via one of said plurality of memory cells.

14. The method of claim 13, wherein each of said plurality of memory cells and each of said second plurality of memory bits is a MRAM memory element.

15. The method of claim 13, wherein each of said plurality of memory cells and each of said second plurality of memory bits is a programmable conductor variable resistance memory element.

16. The method of claim 13, wherein each of said plurality of memory cells and each of said second plurality of memory bits is a phase-changing chalcogenide memory element.