Post last wiring level inductor using patterned plate process

• US 7,732,295 B2
• Filed: 07/10/2008
• Issued: 06/08/2010
• Est. Priority Date: 07/27/2005
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: He, Zhong-Xiang, Gambino, Jeffrey Peter, Stamper, Anthony Kendall, Vaed, Kunal, Coolbaugh, Douglas Duane, Chinthakindi, Anil Kumar, Florkey, John Edward
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US12/170,473
• Publication Number:
  US 20080293210A1
• Time in Patent Office: 698 Days
• Field of Search: 438/381, 438/621, 438/622, 257/E21.022
• US Class Current: 438/381
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/1036 Dual damascene with different via-level and trench-level dielectrics
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An inductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

Claims

1. A method of forming a semiconductor substrate, comprising:

providing a substrate having at least one metal wiring level within the substrate;

depositing a first insulative layer on a surface of the substrate;

forming a portion of a wire bond pad within the first insulative layer;

depositing a second insulative layer on the first insulative layer;

forming an inductor within the second insulative layer using a patterned plate process; and

forming a remaining portion of the wire bond pad within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor,

wherein forming the inductor further comprises;

forming an at least one opening within the second insulative layer;

depositing a liner on the surface of the substrate and on a surface within the at least one opening within the second insulative layer;

depositing a seed layer on a surface of the liner;

removing a portion of the seed layer from the surface of the liner, leaving the seed layer within the at least one opening within the second insulative layer;

depositing a conductive material within the at least one opening within the second insulative layer, such that the conductive material extends above the surface of the substrate; and

planarizing the surface of the substrate to remove excess conductive material extending beyond the surface of the substrate,

wherein between forming the at least one opening within the second insulative layer and depositing the liner, further comprising;

depositing a layer of photoresist on the surface of the substrate; and

forming an at least one opening within the layer of photoresist down to the second insulative layer.

2. The method of claim 1, wherein forming a portion of the wire bond pad within the first insulative layer, further comprises:

forming an at least one opening within the first insulative layer; and

depositing a conductive layer on the surface of the substrate filling the at least one opening within the first insulative layer.

3. The method of claim 2, wherein forming the remaining portion of the wire bond pad, further comprises:

patterning and removing the conductive layer, leaving a wire bond pad region;

depositing a dielectric layer on the surface of the substrate; and

forming an opening within the dielectric layer down to the wire bond pad region.

4. A method of forming a semiconductor substrate, comprising:

providing a substrate having at least one metal wiring level within the substrate;

depositing a first insulative layer on a surface of the substrate;

forming a portion of a wire bond pad within the first insulative layer;

depositing a second insulative layer on the first insulative layer;

forming an inductor within the second insulative layer using a patterned plate process; and

forming a remaining portion of the wire bond pad within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor,

wherein forming the inductor further comprises;

forming an at least one opening within the second insulative layer;

depositing a layer of photoresist on the surface of the substrate;

forming an at least one opening within the layer of photoresist down to the second insulative layer;

depositing a liner on the surface of the substrate and on a surface within the at least one opening within the second insulative layer;

depositing a seed layer on a surface of the liner;

removing a portion of the seed layer from the surface of the liner, leaving the seed layer within the at least one opening within the second insulative layer;

depositing a conductive material within the at least one opening within the second insulative layer, such that the conductive material extends above the surface of the substrate; and

planarizing the surface of the substrate to remove excess conductive material extending beyond the surface of the substrate,

wherein following planarizing the surface of the substrate, further comprising;

removing the layer of photoresist.

5. The method of claim 4, wherein forming a portion of the wire bond pad within the first insulative layer, further comprises:

forming an at least one opening within the first insulative layer; and

depositing a conductive layer on the surface of the substrate filling the at least one opening within the first insulative layer.

6. The method of claim 5, wherein forming the remaining portion of the wire bond pad, further comprises:

patterning and removing the conductive layer, leaving a wire bond pad region;

depositing a dielectric layer on the surface of the substrate; and

forming an opening within the dielectric layer down to the wire bond pad region.