Process for wafer bonding

• US 7,732,299 B2
• Filed: 02/12/2007
• Issued: 06/08/2010
• Est. Priority Date: 02/12/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lai, Tsung-Mu, Chang, Fa-Yuan, Pai, Ching-Chung, Cheng, Chu-Wei, Ho, Chin-Hsiang, Shiau, Gwo-Yuh, Liu, Ming-Chyi, Hsieh, Yuan-Chih, Tsai, Chia-Shiung, Wu, Hua-Shu, Liang, Kai-Chih, Shen, Nick Y. M.
• Primary Examiner(s): Ghyka; Alexander G
• Assistant Examiner(s): Nikmanesh; Seahvosh J
• Application Number:
  US11/673,652
• Publication Number:
  US 20080194076A1
• Time in Patent Office: 1,212 Days
• Field of Search: 438/183, 438/455, 438/926, 257/E21.453
• US Class Current: 438/455
• CPC Class Codes: B81C 1/0038 Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
• CPC Class Codes: B81C 1/00611 Processes for the planarisation of structures planarising depositions C23C, H01L
• CPC Class Codes: B81C 2201/0125 Blanket removal, e.g. polishing
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31056 the removal being a selective chemical etching step, e.g. selective dry etching through a mask
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/926 Dummy metallization

Abstract

The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a top metal layer on a first substrate, in which the top metal layer has a plurality of interconnect features and a first dummy feature; forming a first dielectric layer over the top metal layer; etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer; performing a chemical mechanical polishing (CMP) process over the first dielectric layer; and thereafter bonding the first substrate to a second substrate.

Claims

1. A method for manufacturing a microelectronic device, comprising:

forming a top metal layer on a first substrate, wherein the top metal layer includes a plurality of interconnect features and a first dummy feature;

forming a first dielectric layer over the top metal layer;

etching the first dielectric layer in a target region substantially vertically aligned to the plurality of interconnect features and the first dummy feature of the top metal layer;

performing a chemical mechanical polishing (CMP) process over the etched first dielectric layer; and

after performing the CMP process, bonding the first substrate to a second substrate.

2. The method of claim 1, wherein the first dummy feature is disposed an open region selected from the group consisting of a device region, a scribing-line region, a frame region, and combination thereof.

3. The method of claim 1, further comprising forming a second dummy feature disposed in the first substrate.

4. The method of claim 3, wherein the forming of the second dummy feature comprises forming a structure selected from the group consisting of a dummy gate, a dummy metal feature, a dummy isolation, a dummy device, and combinations thereof.

5. The method of claim 1, further comprising:

forming a plurality of metal-oxide-silicon (MOS) transistors in the first substrate; and

forming the second substrate with a structure selected from the group consisting of a mechanical supporting structure, a micro-electro-mechanical system (MEMS) device, a biosensor, and combinations thereof.

6. The method of claim 1, further comprising forming a patterned photoresist layer over the first dielectric layer having a plurality of openings to expose the first dielectric layer in the target region prior to the etching of the first dielectric layer in the target region.

7. The method of claim 1, further comprising:

forming a second dielectric layer overlying the first dielectric layer, wherein the second dielectric layer is different from the first dielectric layer; and

performing a preliminary CMP process on the second dielectric layer, thereby removing the second dielectric layer within the target region and exposing the first dielectric layer within the target region.

8. A method for manufacturing a microelectronic device, comprising:

forming a first patterned layer on a first substrate, wherein the first patterned layer has a plurality of features;

forming a first material layer on the first patterned layer;

etching the first material layer in a target region substantially vertically aligned over the plurality of features of the first patterned layer;

performing a chemical mechanical polishing (CMP) process on the etched first material layer; and

after performing the CMP process, bonding the first substrate to a second substrate.

9. The method of claim 8, further comprising forming a mask over the first material layer to expose the first material layer in the target region before the etching of the first material layer.

10. The method of claim 9, wherein the forming of the mask comprises forming a patterned photoresist layer on the first material layer, the patterned photoresist layer having a plurality of openings exposing the first material layer within the target region.

11. The method of claim 9, wherein the forming of the mask comprises:

forming a second material layer on and conformal to the first material layer, the second material layer being different form the first material layer; and

performing a preliminary CMP process on the second material layer, thereby removing the second material layer within the target region and exposing the first material layer within the target region.

12. The method of claim 11, wherein the forming of the second material layer includes forming a silicon nitride layer by plasma enhanced chemical vapor deposition (PECVD).

13. The method of claim 11, wherein the second material layer comprises a thickness of about 1K angstrom.

14. The method of claim 11, wherein the performing of the preliminary CMP comprises reducing the second material and first material layers by a thickness ranging between about 2K and 3K angstrom.

15. The method of claim 8, wherein the first material layer comprises silicon oxide formed by high density plasma chemical vapor deposition (HDPCVD).

16. The method of claim 8, wherein the plurality of features comprises top metal features.

17. The method of claim 8, further comprising forming a supplemental layer on the first substrate after the performing of the CMP process and before the bonding.

18. The method of claim 17, wherein the supplemental layer comprises a material selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, and combinations thereof.

19. The method of claim 17, further comprising utilizing an additional CMP process to the supplemental layer.

20. The method of claim 8, further comprising forming a supplemental layer on the first substrate after the etching of the first material layer and before the performing of the CMP process.