FinFET structure using differing gate dielectric materials and gate electrode materials

• US 7,732,874 B2
• Filed: 08/30/2007
• Issued: 06/08/2010
• Est. Priority Date: 08/30/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Zhu, Huilong, Zhang, Ying
• Primary Examiner(s): Purvis; Sue
• Assistant Examiner(s): Sandvik; Benjamin P
• Application Number:
  US11/847,573
• Publication Number:
  US 20090057765A1
• Time in Patent Office: 1,013 Days
• Field of Search: None
• US Class Current: 257/401
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure includes a first finFET and a second finFET. The first finFET and the second finFET may comprise an n-finFET and a p-finFET to provide a CMOS finFET structure. Within the semiconductor structure, at least one of: (1) a first gate dielectric within the first finFET and a second gate dielectric within the second finFET comprise different gate dielectric materials; and/or (2) a first gate electrode within the first finFET and a second gate electrode within the second finFET comprise different gate electrode materials.

Claims

1. A semiconductor structure comprising:

a first finFET including a first semiconductor fin located over a substrate, a first gate dielectric located upon the first semiconductor fin and a first gate electrode located to straddle the first semiconductor fin and to provide a first channel region beneath the first gate electrode that separates a plurality of source and drain regions within the first semiconductor fin; and

a second finFET including a second semiconductor fin located over the substrate, a second gate dielectric located upon the second semiconductor fin and a second gate electrode located to straddle the second semiconductor fin and to provide a second channel region beneath the second gate electrode that separates a plurality of source and drain regions within the second semiconductor fin, wherein each of the first finFET and the second finFET comprises an n-finFET and one of the first gate dielectric or the second gate dielectric is located on the sidewalls and atop its corresponding semiconductor fin, while the other of the first gate dielectric or the second gate dielectric is located only on the sidewalls of its corresponding semiconductor fin and where at least either;

the first gate dielectric and the second gate dielectric comprise different gate dielectric materials;

or

the first gate electrode and the second gate electrode comprise different gate electrode materials.

2. The CMOS structure of claim 1 wherein the substrate comprises a dielectric surface.

3. The CMOS structure of claim 1 wherein the substrate comprises a dielectric surface layer located upon a semiconductor substrate.

4. The CMOS structure of claim 1 wherein the first gate dielectric and the second gate dielectric comprise different gate dielectric materials.

5. The CMOS structure of claim 1 wherein the first gate electrode and the second gate electrode comprise different gate electrode materials.

6. The CMOS structure of claim 1 wherein:

the first gate dielectric and the second gate dielectric comprise different gate dielectric materials; and

the first gate electrode and the second gate electrode comprise different gate electrode materials.

7. The CMOS structure of claim 1 wherein the first gate electrode is contiguous with the second gate electrode.

8. The CMOS structure of claim 1 wherein the first gate electrode is not contiguous with the second gate electrode.

9. A semiconductor structure comprising:

a first finFET including a first semiconductor fin located over a substrate, a first gate dielectric located upon the first semiconductor fin and a first gate electrode located to straddle the first semiconductor fin and to provide a first channel region beneath the first gate electrode that separates a plurality of source and drain regions within the first semiconductor fin; and

a second finFET including a second semiconductor fin located over the substrate, a second gate dielectric located upon the second semiconductor fin and a second gate electrode located to straddle the second semiconductor fin and to provide a second channel region beneath the second gate electrode that separates a plurality of source and drain regions within the second semiconductor fin, wherein each of the first finFET and the second finFET comprises a p-finFET and one of the first gate dielectric or the second gate dielectric is located on the sidewalls and atop its corresponding semiconductor fin, while the other of the first gate dielectric or the second gate dielectric is located only on the sidewalls of its corresponding semiconductor fin and where at least either;

the first gate dielectric and the second gate dielectric comprise different gate dielectric materials;

or

the first gate electrode and the second gate electrode comprise different gate electrode materials.

10. A method for fabricating a semiconductor structure comprising:

forming over a substrate a first finFET that includes a first semiconductor fin formed over the substrate, a first gate dielectric formed upon the first semiconductor fin and a first gate electrode formed to straddle the first semiconductor fin and to provide a first channel region beneath the first gate electrode that separates a plurality of source and drain regions within the first semiconductor fin; and

forming over the substrate a second finFET that includes a second semiconductor fin formed over the substrate, a second gate dielectric formed upon the second semiconductor fin and a second gate electrode formed to straddle the second semiconductor fin and to provide a second channel region beneath the second gate electrode that separates a plurality of source and drain regions within the second semiconductor fin, wherein each of the first finFET and the second finFET comprises an n-finFET or a n-finFET and one of the first gate dielectric or the second gate dielectric is located on the sidewalls and atop its corresponding semiconductor fin, while the other of the first gate dielectric or the second gate dielectric is located only on the sidewalls of its corresponding semiconductor fin and where at least either;

the first gate dielectric and the second gate dielectric comprise different gate dielectric materials;

or

the first gate electrode and the second gate electrode comprise different gate electrode materials.

11. The method of claim 10 wherein the forming over the substrate the first finFET and the second finFET provides the first gate electrode separate from the second gate electrode.

12. The method of claim 10 wherein the forming over the substrate the first finFET and the second finFET provides the first gate electrode contiguous with the second gate electrode.

13. A method for fabricating a semiconductor structure comprising:

forming a first semiconductor fin and a second semiconductor fin over a substrate;

forming a first gate dielectric upon the first semiconductor fin and first gate electrode upon the first gate dielectric to define the locations of a channel and a plurality of source and drain regions within the first semiconductor fin;

forming a second gate dielectric different than the first gate dielectric upon the second semiconductor fin and a second gate electrode different than the first gate electrode upon the second gate dielectric to define the locations of a channel and a plurality of source and drain regions within the second semiconductor fin, wherein one of the first gate dielectric or the second gate dielectric is located on the sidewalls and atop its corresponding semiconductor fin, while the other of the first gate dielectric or the second gate dielectric is located only on the sidewalls of its corresponding semiconductor fin and wherein;

the first semiconductor fin is included within a p-finFET;

the first gate dielectric comprises a comparatively low dielectric constant material;

the first gate electrode does not include a metal material;

the second semiconductor fin is included within an n-finFET;

the second gate dielectric comprises a comparatively high dielectric constant material; and

the second gate electrode includes a metal material.

14. The method of claim 13 wherein the first semiconductor fin is formed simultaneously with the second semiconductor fin.

15. The method of claim 13 wherein the first gate is separate from the second gate.

16. The method of claim 13 wherein the first gate is contiguous with the second gate.