Power transistor with trench sinker for contacting the backside

• US 7,732,876 B2
• Filed: 02/27/2008
• Issued: 06/08/2010
• Est. Priority Date: 08/03/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Dolny, Gary M., Grebs, Thomas E.
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US12/038,184
• Publication Number:
  US 20080142883A1
• Time in Patent Office: 832 Days
• Field of Search: 257330-333, 257/341, 257/401, 438135-138, 438/172, 438/243, 438268-270
• US Class Current: 257/401
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A power transistor includes a first semiconductor region of a first conductivity type extending over and in contact with a second semiconductor region of the first conductivity type. Gate trenches extend into the first semiconductor region. Well regions of a second conductivity type extend over the first semiconductor region and between adjacent gate trenches. A sinker trench extends through the first semiconductor region and terminates within the second semiconductor region, and is laterally spaced from an outer one of the gate trenches with no well regions abutting sidewalls of the sinker trench. Source regions of the first conductivity type extend over the well regions. A conductive material in the sinker trench makes electrical contact with the second semiconductor region along the bottom of the sinker trench and with a drain interconnect layer extending along the top of the sinker trench.

Claims

1. A trench power transistor comprising:

a first semiconductor region of a first conductivity type extending over and in contact with a second semiconductor region of the first conductivity type, the first semiconductor region having a lower dopant concentration than the second semiconductor region;

a plurality of gate trenches extending into the first semiconductor region, each gate trench including a gate electrode and a gate dielectric layer lining sidewalls of each gate trench;

well regions of a second conductivity type over and in contact with the first semiconductor region, each well region extending between and abutting every two adjacent gate trenches;

a sinker trench extending through the first semiconductor region and terminating within the second semiconductor region, the sinker trench being laterally spaced from an outer one of the plurality of gate trenches, with no well regions abutting sidewalls of the sinker trench;

source regions of the first conductivity type over and in contact with the well regions, the source regions flanking the gate trenches; and

a conductive material in the sinker trench making electrical contact with the second semiconductor region along the bottom of the sinker trench and making electrical contact with a drain interconnect layer extending along the top of the sinker trench.

2. The transistor of claim 1 wherein the plurality of gate trenches terminate within the first semiconductor region.

3. The transistor of claim 1 wherein the plurality of gate trenches extend into and terminate within the second semiconductor region.

4. The transistor of claim 1 wherein the first semiconductor region is an epitaxial layer and the second semiconductor region is a substrate.

5. The transistor of claim 1 wherein one of the well regions extends between the outer one of the plurality of gate trenches and the sinker trench but does not abut the sinker trench.

6. The transistor of claim 1 wherein the conductive material electrically contacts the first semiconductor region along sidewalls of the sinker trench.

7. The transistor of claim 1 further comprising a sinker dielectric layer lining sidewalls of the sinker trench.

8. The transistor of claim 7 wherein the sinker dielectric layer includes one of oxide, silicon nitride, multilayer of oxide and nitride, silicon oxynitride, a low k insulating material or a high k insulating material.

9. The transistor of claim 7 wherein the sinker dielectric layer is thicker than the gate dielectric layer.

10. The transistor of claim 7 wherein the sinker dielectric layer and the gate dielectric layer have the same thickness.

11. The transistor of claim 1 wherein each gate trench further includes a thick bottom dielectric below the gate electrode, the thick bottom dielectric having a greater thickness than that of the gate dielectric.

12. The transistor of claim 1 wherein each gate trench includes a shield electrode below the gate electrode, the gate and shield electrodes being insulated from one another.

13. The transistor of claim 1 wherein a spacing between the sinker trench and the outer one of the plurality of gate trenches is greater than a spacing between every two adjacent gate trenches.

14. The transistor of claim 1 further comprising a source interconnect layer contacting the source regions, and a gate interconnect layer contacting the gate electrode in each gate trench, wherein all of the drain, source and gate interconnect layers extend over the first semiconductor region.

15. The transistor of claim 14 further comprising a back-side metal layer extending along a bottom surface of the second semiconductor region.

16. The transistor of claim 1 wherein the sinker trench has a width greater a width of each gate trench.

17. The transistor of claim 1 wherein a ratio of a width of the sinker trench to a width of each gate trench is less than ten to one.

18. The transistor of claim 1 wherein the conductive material comprises polysilicon and a ratio of a width of the sinker trench to a width of each gate trench is less than five to one.

19. The transistor of claim 1 wherein the conductive material comprises a metal and a ratio of a width of the sinker trench to a width of each gate trench is less than three to one.

20. The transistor of claim 1 wherein the conductive material includes one or more of doped polysilicon, selective epitaxial silicon (SEG), metal, or metallic compound.