Etch singulated semiconductor package

• US 7,732,899 B1
• Filed: 02/04/2009
• Issued: 06/08/2010
• Est. Priority Date: 12/02/2005
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Berry, Christopher J., Scanlan, Christopher M., Faheem, Faheem F.
• Primary Examiner(s): Zarneke; David A
• Application Number:
  US12/365,682
• Time in Patent Office: 489 Days
• Field of Search: 257/E23.054, 257/666
• US Class Current: 257/666
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In accordance with the present invention, there is provided various methods of simultaneously fabricating a plurality of semiconductor packages (e.g., cavity type semiconductor packages) wherein the singulation process is achieved using etching techniques as opposed to more conventional cutting techniques such as sawing or punching. Such etching techniques are inherently lower in cost and free from many of the defects induced by other cutting techniques.

Claims

1. A semiconductor package, comprising:

a die pad having opposed top and bottom surfaces and a peripheral edge;

a plurality of leads disposed in spaced relation to the die pad, each of the leads having opposed top and bottom surfaces, an inner end and an outer end;

plating layers applied to at least portions of the bottom surfaces of the die pad and the leads, each of the plating layers applied to the leads having an outer end;

a semiconductor die attached to the die pad and electrically connected to at least some of the leads; and

a package body having bottom and side surfaces, the package body at least partially encapsulating the die pad, the leads, the plating layers and the semiconductor die;

the outer end of each of the leads being recessed relative to the outer end of the plating layer applied to the bottom surface thereof and to the side surface of the package body.

2. The semiconductor package of claim 1 wherein the plating layer applied to the bottom surface of the die pad terminates inwardly from the peripheral edge thereof, and the plating layers applied to the bottom surfaces of the leads terminate inwardly from the inner ends of respective ones of the leads.

3. The semiconductor package of claim 1 wherein the plating layer applied to the bottom surface of the die pad terminates inwardly from the peripheral edge thereof.

4. The semiconductor package of claim 1 wherein the plating layers applied to the bottom surfaces of the leads terminate inwardly from the inner ends of respective ones of the leads.

5. The semiconductor package of claim 1 wherein the semiconductor die is electrically connected to the leads by conductive wires which are encapsulated by the package body.

6. The semiconductor package of claim 1 wherein each of the plating layers defines a bottom surface which extends in generally co-planar relation to the bottom surface of the package body.

7. The semiconductor package of claim 1 further comprising a second semiconductor die stacked upon and attached to the semiconductor die, the second semiconductor die being electrically connected to the semiconductor die and at least partially encapsulated by the package body.

8. The semiconductor package of claim 7 wherein the second semiconductor die is electrically connected to the semiconductor die by conductive wires which are encapsulated by the package body.

9. The semiconductor package of claim 8 wherein the semiconductor die is electrically connected to the leads by conductive wires which are encapsulated by the package body.

10. A semiconductor package, comprising:

a plurality of leads, each of the leads having opposed top and bottom surfaces, an inner end and an outer end;

plating layers applied to at least portions of the bottom surfaces of the leads, each of the plating layers having an outer end;

a semiconductor die electrically connected to at least some of the leads; and

a protective structure having bottom and side surfaces, the protective structure at least partially covering the leads, the plating layers, and the semiconductor die;

the outer end of each of the leads being recessed relative to the outer end of the plating layer applied to the bottom surface thereof and to the side surface of the protective structure.

11. The semiconductor package of claim 10 wherein the plating layers applied to the bottom surfaces of the leads terminate inwardly from the inner ends of respective ones of the leads.

12. The semiconductor package of claim 10 wherein the semiconductor die is electrically connected to the leads by conductive wires which are covered by the protective structure.

13. The semiconductor package of claim 10 wherein each of the plating layers defines a bottom surface which extends in generally co-planar relation to the bottom surface of the protective structure.

14. The semiconductor package of claim 10 further comprising a second semiconductor die stacked upon and attached to the semiconductor die, the second semiconductor die being electrically connected to semiconductor die and at least partially covered by the protective structure.

15. The semiconductor package of claim 10 wherein the protective structure is a package body which at least partially encapsulates the leads and the semiconductor die.

16. The semiconductor package of claim 10 the semiconductor die is mounted to a die pad which is partially covered by the protective structure.

17. The semiconductor package of claim 16 wherein the die pad has a bottom surface which includes one of the plating layers applied to at least a portion thereof.

18. A semiconductor package, comprising:

a plurality of leads, each of the leads having opposed top and bottom surfaces, and an outer end;

plating layers applied to at least portions of the bottom surfaces of the leads, each of the plating layers having an outer end;

a semiconductor die electrically connected to at least some of the leads; and

a protective structure at least partially covering the leads, the plating layers, and the semiconductor die;

the outer end of each of the leads being recessed relative to the outer end of the plating layer applied to the bottom surface thereof.

19. The semiconductor package of claim 18 wherein the protective structure has a side surface, and the outer end of each of the leads is further recessed relative to the side surface of the protective structure.

20. The semiconductor package of claim 19 wherein the protective structure is a package body which at least partially encapsulates the leads, the plating layers, and the semiconductor die.