Transistor arrangement, integrated circuit and method for operating field effect transistors

• US 7,733,156 B2
• Filed: 09/01/2004
• Issued: 06/08/2010
• Est. Priority Date: 09/04/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Thewes, Roland, Koh, Jeongwook, Brederlow, Ralf
• Primary Examiner(s): Pert; Evan
• Application Number:
  US10/570,924
• Publication Number:
  US 20070176634A1
• Time in Patent Office: 2,106 Days
• Field of Search: 327/378, 327/379, 327/389
• US Class Current: 327/378
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 2203/21178 Power transistors are made by coupling a plurality of single transistors in parallel
• CPC Class Codes: H03F 2203/7215 the gated amplifier being switched on or off by a switch at the input of the amplifier
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.

Claims

1. A transistor arrangement comprising:

a first and a second field effect transistor, each of which has a first and a second source/drain terminal and a control terminal for application of a first or a second signal, the two field effect transistors being of the same conduction type;

wherein the transistor arrangement is configured such that alternately;

the first signal can be applied to the control terminal of the first field effect transistor and, simultaneously, the second signal can be applied to the control terminal of the second field effect transistor; and

the second signal can be applied to the control terminal of the first field effect transistor and, simultaneously, the first signal can be applied to the control terminal of the second field effect transistor;

wherein one of the first and second signals is a useful signal and the respective other signal is a reference potential, or in which the first signal and the second signal are in each case a reference potential, or in which the first signal and the second signal are in each case a useful signal.

2. The transistor arrangement as claimed in claim 1, wherein the first source/drain terminals of the first and of the second field effect transistor are coupled to one another;

and wherein second source/drain terminals of the first and of the second field effect transistor are coupled to one another.

3. The transistor arrangement as claimed in claim 1, wherein the control terminal is a gate terminal or a substrate terminal.

4. The transistor arrangement as claimed in claim 3, wherein at least one of the substrate terminals is set up as a well terminal of one of the two field effect transistors, which is formed in a well.

5. The transistor arrangement as claimed in claim 1, wherein, for the case where the control terminal of the first and of the second field effect transistor is a gate terminal, the first and the second field effect transistor have a substrate terminal as additional control terminal;

wherein for the case where the control terminal of the first and of the second field effect transistor is a substrate terminal, the first and the second field effect transistor have a gate terminal as additional control terminal, and wherein the additional control terminals of the first and of the second field effect transistor are coupled to one another.

6. The transistor arrangement as claimed in claim 1, wherein the first and the second field effect transistor are structurally identical.

7. A transistor arrangement comprising:

a first and a second field effect transistor, each of which has a first and a second source/drain terminal and a control terminal for application of a first or a second signal, the two field effect transistors being of the same conduction type;

wherein the transistor arrangement is configured such that alternately;

the first signal can be applied to the control terminal of the first field effect transistor and, simultaneously, the second signal can be applied to the control terminal of the second field effect transistor; and

the second signal can be applied to the control terminal of the first field effect transistor and, simultaneously, the first signal can be applied to the control terminal of the second field effect transistor;

wherein the first and the second signal are applied alternately to the control terminals of the first and second field effect transistors with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the field effect transistors.

8. The transistor arrangement as claimed in claim 7, wherein the first and the second signal are applied alternately to the control terminals of the first and second field effect transistors with an alternating frequency which is greater than the frequencies of a useful frequency band of an assigned circuit.

9. The transistor arrangement as claimed in claim 7, wherein the first and the second signal are applied alternately to the control terminals of the first and second field effect transistors with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the field effect transistors.

10. The transistor arrangement as claimed in claim 7, wherein the arrangement is configured such that a respective one of the two field effect transistors can be operated at an inversion operating point and the respective other of the two field effect transistors can be operated at an accumulation or depletion operating point.

11. A transistor arrangement comprising:

a first and a second field effect transistor, each of which has a first and a second source/drain terminal and a control terminal for application of a first or a second signal, the two field effect transistors being of the same conduction type;

wherein the transistor arrangement is configured such that alternately;

the first signal can be applied to the control terminal of the first field effect transistor and, simultaneously, the second signal can be applied to the control terminal of the second field effect transistor; and

the second signal can be applied to the control terminal of the first field effect transistor and, simultaneously, the first signal can be applied to the control terminal of the second field effect transistor;

wherein the control terminal of the first field effect transistor is coupled to a first switching element, which can be switched by means of a first clock signal with an alternating frequency;

wherein, the control terminal of the second field effect transistor is coupled to a second switching element, which can be switched by means of a second clock signal, which is complementary to the first clock signal, with the alternating frequency; and

wherein, by means of the respective switching element, the first or the second signal is alternately applied to the respective control terminal of the respective field effect transistor with the alternating frequency.

12. The transistor arrangement as claimed in claim 11, wherein the first and second switching elements are first and second switching transistor arrangements, to the respective gate terminal of which the respective clock signal can be applied, and a respective source/drain terminal of a respective switching transistor being coupled to the control terminal of the respective field effect transistor.

13. The transistor arrangement as claimed in claim 11, wherein the arrangement is configured as a differential transistor arrangement, in which the first signal and the second signal are differential useful signals with respect to one another.

14. The transistor arrangement as claimed in claim 13 further comprising a low-pass filter, which is connected up in such a way that an interference signal caused by means of the alternating application of the first signal and of the second signal can be suppressed by means of the low-pass filter.

15. The transistor arrangement as claimed in claim 13, wherein the first source/drain terminal of the first field effect transistor is coupled to a third switching element, which can be switched by means of the first clock signal with the alternating frequency, and wherein the first source/drain terminal of the second field effect transistor is coupled to a fourth switching element, which can be switched by means of the second clock signal, which is complementary to the first clock signal, with the alternating frequency.

16. The transistor arrangement as claimed in claim 13 further comprising a current source, which is coupled to the first source/drain terminal of the first field effect transistor and to the first source/drain terminal of the second field effect transistor.

17. The transistor arrangement as claimed in claim 13, wherein the second source/drain terminal of the first field effect transistor is coupled to a fifth switching element, which can be switched by means of the first clock signal with the alternating frequency;

and wherein the second source/drain terminal of the second field effect transistor is coupled to a sixth switching element, which can be switched by means of the second clock signal, which is complementary to the first clock signal, with the alternating frequency.

18. The transistor arrangement as claimed in one of claim 13, wherein the arrangement is formed on and/or in a silicon on insulator substrate.

19. The transistor arrangement as claimed in claim 18, further comprising at least one additional field effect transistor, wherein each of the at least one additional field effect transistor having a first and a second source/drain terminal and having a control terminal, to which the first or the second signal can be applied, and wherein the transistor arrangement being set up in such a way that, in a first operating state, the first signal is applied to the control terminal of the first field effect transistor or of the second field effect transistor or of precisely one of the at least one additional field effect transistor and, simultaneously, the second signal is applied to the control terminals of all of the other field effect transistors, in subsequent operating states the first signal being applied progressively to the control terminal of in each case one of the remaining field effect transistors and, simultaneously, the second signal being applied to the control terminals of all of the other field effect transistors.

20. The transistor arrangement as claimed in one of claim 13, wherein the arrangement is realized using analog circuit technology.

21. The transistor arrangement as claimed in claim 11 further comprising a clock generator unit, which is coupled to the field effect transistors in such a way that it provides the signals to the field effect transistors alternately by means of clock signals that are shifted relative to one another.

22. The transistor arrangement as claimed in claim 21, wherein the clock generator unit is set up in such a way that it prescribes the clock signals for reducing the heating of the field effect transistors formed on and/or in the silicon on insulator substrate and/or for reducing the floating body effect of the field effect transistors formed on and/or in the silicon on insulator substrate.

23. A method for operating field effect transistors comprising:

connecting a first and a second field effect transistor to one another, each of the field effect transistors having a first and a second source/drain terminal and having a control terminal for application of a first or a second signal, the two field effect transistors being of the same conduction type;

setting up the transistor arrangement such that alternately the first signal is applied to the control terminal of the first field effect transistor and, simultaneously, the second signal is applied to the control terminal of the second field effect transistor and the second signal is applied to the control terminal of the first field effect transistor and, simultaneously, the first signal is applied to the control terminal of the second field effect transistor; and

alternately applying the first and second signals such that the quasi-Fermi energy in a boundary region between channel region and gate insulating layer of the field effect transistors is periodically altered by a value which is greater than the product of the Boltzmann constant and the absolute temperature.

24. The method as claimed in claim 23 further comprising using a gate terminal or a substrate terminal as the control terminal.

25. The method as claimed in claim 24 further comprising alternately applying the first and second signals such that the quasi-Fermi energy in a boundary region between channel region and gate insulating layer of the field effect transistors is periodically altered by between approximately 100 meV and approximately 1 eV.