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Method of fabricating a liquid crystal display device using a three mask process and double layer electrodes

  • US 7,733,453 B2
  • Filed: 12/21/2005
  • Issued: 06/08/2010
  • Est. Priority Date: 12/31/2004
  • Status: Active Grant
First Claim
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1. A method of fabricating a liquid crystal display device, comprising:

  • a first mask process forming a first mask pattern group including a gate line, a gate electrode connected to the gate line and a common line parallel to the gate line having at least first double conductive layers, the first double conductive layers having a first conductive layer made of transparent conductive material and a second conductive layer thereon made of opaque metal material, and a common electrode formed by an extension of the first conductive layer of the common line on a substrate;

    a second mask process forming a gate insulating film on the first mask pattern group and a semiconductor pattern on the gate insulating film; and

    a third mask process forming a third mask pattern group including a data line, a source electrode connected to the data line and a drain electrode opposed to the source electrode having at least second double conductive layers, the second double conductive layers having a third conductive layer made of transparent material and a fourth conductive layer thereon made of opaque metal, and a pixel electrode formed by an extension of the third conductive layer of the drain electrode and overlapped with the common electrode, on the gate insulating film,wherein the common electrode and the pixel electrode are formed at pixel area defined by the gate line and the data line; and

    wherein the common electrode is formed at the whole region the pixel area, and the pixel electrode is partially formed with a plurality of ribs at the pixel area,wherein the first mask process includes;

    forming the first double conductive layers on the substrate;

    forming a first photo-resist pattern having step coverage by a photolithography using one of a half tone mask and a diffraction exposure mask;

    forming the first mask pattern group including the gate line, the gate electrode, the common line, and a lower pad electrode having the first double conductive layers by an etching process using the first photo-resist pattern;

    partially removing the first photo-resist pattern to expose the second conductive layer of the first double conductive layers and etching the exposed second conductive layer using the remaining first photo-resist pattern to expose the first conductive layer of the first double conductive layers such that the common electrode is formed from the first conductive layer; and

    removing the remaining first photo-resist pattern,wherein the third mask process includes;

    forming the second double conductive layers on the gate insulating film provided with the semiconductor pattern;

    forming a third photo-resist pattern having step coverage using one of a half tone mask and a diffractive exposure mask;

    patterning the second double conductive layers by an etching process using the third photo-resist pattern to provide a third mask pattern group including the data line, the source electrode, and the drain electrode;

    removing an amorphous silicon layer doped with an impurity exposed between the source electrode and drain electrode; and

    partially removing the third photo-resist pattern to expose the fourth conductive layer of the second double conductive layers and etching the exposed third photo-resist pattern using the remaining third photo-resist pattern to expose the third conductive layer of the second double conductive layers such that the pixel electrode and the upper pad electrode are formed from the third conductive layer; and

    removing the remaining third photo-resist pattern.

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