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Energy conditioning circuit arrangement for integrated circuit

DC CAFC
  • US 7,733,621 B2
  • Filed: 09/27/2009
  • Issued: 06/08/2010
  • Est. Priority Date: 04/08/1997
  • Status: Expired due to Fees
First Claim
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1. A conductive pathway arrangement for an integrated circuit wafer, comprising:

  • an integrated circuit wafer;

    a first conductive pathway having a first area;

    a second conductive pathway having a second area, and wherein said second conductive pathway is connected to said integrated circuit wafer;

    a third conductive pathway having a third area;

    a fourth conductive pathway having a fourth area, and wherein said fourth conductive pathway is connected to said integrated circuit wafer;

    a fifth conductive pathway having a fifth area;

    a dielectric;

    wherein said dielectric spaces apart all said conductive pathways of said conductive pathway arrangement from one another;

    wherein said first conductive pathway, said third conductive pathway and said fifth conductive pathway are conductively connected to one another;

    wherein said second conductive pathway is conductively isolated from said first conductive pathway;

    wherein said third area of said third conductive pathway is positioned between a first portion of said second area of said second conductive pathway and a first portion of said fourth area of said fourth conductive pathway; and

    wherein said first portion of said second area of said second conductive pathway is aligned with said first portion of said fourth area of said fourth conductive pathway.

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