Energy conditioning circuit arrangement for integrated circuit

• US 7,733,621 B2
• Filed: 09/27/2009
• Issued: 06/08/2010
• Est. Priority Date: 04/08/1997
• Status: Expired due to Fees

• Current Assignee: X2Y Attenuators, LLC
• Original Assignee: X2Y Attenuators, LLC
• Inventors: Anthony, Anthony A., Anthony, William M.
• Primary Examiner(s): Jackson; Stephen W
• Application Number:
  US12/567,777
• Publication Number:
  US 20100078199A1
• Time in Patent Office: 254 Days
• Field of Search: 361/118
• US Class Current: 361/118
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/023 : using auxiliary mounted passive components or auxiliary substances printed passive components H05K1/16
• CPC Class Codes: H05K 1/0237 : High frequency adaptations H05K1/0216 takes precedence
• CPC Class Codes: H05K 2201/09236 : Parallel layout
• CPC Class Codes: H05K 2201/10378 : Interposers
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing

Abstract

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

Claims

1. A conductive pathway arrangement for an integrated circuit wafer, comprising:

an integrated circuit wafer;

a first conductive pathway having a first area;

a second conductive pathway having a second area, and wherein said second conductive pathway is connected to said integrated circuit wafer;

a third conductive pathway having a third area;

a fourth conductive pathway having a fourth area, and wherein said fourth conductive pathway is connected to said integrated circuit wafer;

a fifth conductive pathway having a fifth area;

a dielectric;

wherein said dielectric spaces apart all said conductive pathways of said conductive pathway arrangement from one another;

wherein said first conductive pathway, said third conductive pathway and said fifth conductive pathway are conductively connected to one another;

wherein said second conductive pathway is conductively isolated from said first conductive pathway;

wherein said third area of said third conductive pathway is positioned between a first portion of said second area of said second conductive pathway and a first portion of said fourth area of said fourth conductive pathway; and

wherein said first portion of said second area of said second conductive pathway is aligned with said first portion of said fourth area of said fourth conductive pathway.

2. The conductive pathway arrangement of claim 1, wherein said second conductive pathway is conductively isolated from said fourth conductive pathway.

3. The conductive pathway arrangement of claim 2, wherein said first portion of said second area of said second conductive pathway is shielded from said first portion of said fourth area of said fourth conductive pathway by said third area of said third conductive pathway.

4. The conductive pathway arrangement of claim 3, wherein said first conductive pathway, said third conductive pathway and said fifth conductive pathway are connected to at least one conductive VIA.

5. The conductive pathway arrangement of claim 3, wherein said first conductive pathway is a first conductive feed-thru pathway, and wherein said second conductive pathway is a second conductive feed-thru pathway;

and

wherein said conductive pathway arrangement is operable as an energy conditioning network when said conductive pathway arrangement is energized.

6. An energized conductive pathway arrangement of claim 5.

7. An energized conductive pathway arrangement of claim 4, wherein said second conductive pathway is a first differential feed-thru pathway, and wherein said fourth conductive pathway is a second differential feed-thru pathway, and wherein at least said first portion of said second area of said first differential feed-thru pathway and said first portion of said fourth area of said second differential feed-thru pathway operate together to modify an electrical transmission of energy.

8. The conductive pathway arrangement of claim 4, wherein said first portion of said second area of said second conductive pathway is substantially the same size as said first portion of said fourth area of said fourth conductive pathway.

9. An energized conductive pathway arrangement of claim 3, wherein said third area of said third conductive pathway sustains a first voltage for a first energy propagating said first portion of said second area of said second conductive pathway;

and

wherein said third area of said third conductive pathway sustains said first voltage for a second energy propagating said first portion of said fourth area of said fourth conductive pathway.

10. An electrode arrangement comprising:

a first differential electrode and a second differential electrode, and wherein said differential electrodes are electrically isolated from each other;

a first common electrode, a second common electrode and a third common electrode, and wherein said common electrodes are conductively connected to one another;

wherein said common electrodes are electrically isolated from said differential electrodes;

wherein a portion of said second common electrode is between a portion of said first differential electrode and a portion of said second differential electrode, and wherein said portion of said first differential electrode, said portion of said second common electrode and said portion of said second differential electrode are between a portion of said first common electrode and a portion of said third common electrode, and wherein any said portion of said common electrodes and any said portion of said differential electrodes are substantially parallel with one another;

wherein a first area of said portion of said second common electrode is larger than an area of said portion of said first differential electrode, and wherein a second area of said portion of said second common electrode is larger than an area of said portion of said second differential electrode;

wherein said area of said portion of said first differential electrode is in an alignment with said area of said portion of said second differential electrode, and wherein said area of said portion of said first differential electrode overlaps said area of said portion of said second differential electrode;

wherein said area of said portion of said first differential electrode and said area of said portion of said second differential electrode are simultaneously shielded from each other by said first area of said portion of said second common electrode and said second area of said portion of said second common electrode; and

wherein said area of said portion of said first differential electrode and said area of said portion of said second differential electrode are simultaneously shielded by said portion of said first common electrode and said portion of said third common electrode.

11. The electrode arrangement of claim 10, further comprising:

an integrated circuit die; and

wherein said first differential electrode is conductively connected to a first part of said integrated circuit die, and wherein said second differential electrode is conductively connected to a second part of said integrated circuit die.

12. The electrode arrangement of claim 11, wherein said first area of said portion of said second common electrode is substantially the same size as said second area of said portion of said second common electrode.

13. The electrode arrangement of claim 11, wherein each common electrode of said common electrodes is larger than any one differential electrode of said differential electrodes.

14. An energized electrode arrangement of claim 12, further comprising:

a first capacitance having a first capacitive value, wherein said first capacitance is operable between said area of said portion of said first differential electrode and said first area of said portion of said second common electrode;

a second capacitance having a second capacitance value, wherein said second capacitance is operable between said area of said portion of said second differential electrode and said second area of said portion of said second common electrode;

a third capacitance having a third capacitance value, and wherein said third capacitance is operable between said area of said portion of said first differential electrode and said area of said portion of said second differential electrode; and

wherein said third capacitance value is substantially half of said first capacitance value.

15. The electrode arrangement of claim 12, wherein said arrangement is operable as an energy conditioning network when said electrode arrangement is energized.

16. The electrode arrangement of claim 13, wherein said common electrodes provide simultaneous electrostatic shielding of said area of said portion of said first differential electrode and said area of said portion of said second differential electrode when said electrode arrangement is energized.

17. A substrate arrangement for an integrated circuit die, comprising:

a substrate having at least a first and a second substrate surface, and wherein said first substrate surface and said second substrate surface are parallel with each other;

a first common electrode having a first common electrode layered portion;

a first electrode having a first electrode layered portion;

a second common electrode having a second common electrode layered portion;

a second electrode having a second electrode layered portion;

a third common electrode having a third common electrode layered portion;

wherein said first common electrode is electrically isolated from said first electrode and said second electrode, and wherein said first electrode and said second electrode are electrically isolated from each other;

wherein an area of said second common electrode layered portion is between an area of said first electrode layered portion and an area of said second electrode layered portion, and wherein said area of said first electrode layered portion, said area of said second common electrode layered portion, and said area of said second electrode layered portion are between an area of said first common electrode layered portion and an area of said third common electrode layered portion, and wherein said area of said first common electrode layered portion, said area of said first electrode layered portion, said area of said second common electrode layered portion, said area of said second electrode layered portion, and said area of said third common electrode layered portion are between said first substrate surface and said second substrate surface;

wherein said area of said first common electrode layered portion is larger than said area of said first electrode layered portion, and wherein said area of said second common electrode layered portion is larger than said area of said first electrode layered portion, and wherein said area of said third common electrode layered portion is larger than said area of said first electrode layered portion; and

wherein said area of said first electrode layered portion is shielded from said area of said second electrode layered portion by said area of said second common electrode layered portion.

18. The substrate arrangement of claim 17, further comprising:

an integrated circuit die connected to said first substrate surface;

wherein said first electrode is conductively connected to said integrated circuit die;

wherein said second electrode is conductively connected to said integrated circuit die; and

wherein said three common electrodes are conductively connected to one another.

19. The substrate arrangement of claim 18, wherein said area of said first common electrode layered portion is larger than said area of said second electrode layered portion, and wherein said area of said second common electrode layered portion is larger than said area of said second electrode layered portion, and wherein said area of said third common electrode layered portion is larger than said area of said second electrode layered portion.

20. An energized substrate arrangement of claim 19, wherein said first electrode and said second electrode are each operable in a feed-thru configuration;

and

wherein at least all of said areas of all said layered portions are operable together as one differential mode and common mode energy filter.