Semiconductor memory device and method of operating same

• US 7,733,693 B2
• Filed: 04/08/2008
• Issued: 06/08/2010
• Est. Priority Date: 05/13/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Innovative Silicon ISI SA
• Inventors: Bron, Michel, Ferrant, Richard, Carman, Eric, Okhonin, Serguei
• Primary Examiner(s): Dinh, Son
• Application Number:
  US12/082,020
• Publication Number:
  US 20080205114A1
• Time in Patent Office: 791 Days
• Field of Search: 365/177, 365/63, 365/181, 365/230.03
• US Class Current: 365/177
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 2211/4065 Low level details of refresh operations
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

Claims

1. A semiconductor memory cell array, comprising:

a plurality of dynamic random access memory cells arranged in a matrix of rows and columns, each dynamic random access memory cell includes at least one transistor having;

a first region, a second region, a body region disposed between the first region and the second region, wherein the body region is electrically floating, and a gate spaced apart from the body region;

wherein each memory cell includes (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell; and

wherein;

the first region of the transistor of each memory cell corresponding to a first row of dynamic random access memory cells is connected to a first source line,

the first region of the transistor of each memory cell corresponding to a second row of dynamic random access memory cells is connected to second source line, and

the first region of the transistor of each memory cell corresponding to a third row of dynamic random access memory cells is connected to a third source line;

wherein the first row of memory cells is adjacent to both the second and third rows of memory cells; and

wherein the second region of the transistor of each memory cell of the first row of dynamic random access memory cells shares the second region with the transistor of an adjacent memory cell of the second row of dynamic random access memory cells.

2. The semiconductor memory cell array of claim 1 wherein:

the second region of the transistor of each memory cell of the first row of dynamic random access memory cells is connected to an associated bit line; and

the second region of the transistor of a memory cell of the second row of dynamic random access memory cells which is adjacent to a memory cell of the first row of dynamic random access memory cells is connected to the to the bit line associated with the adjacent memory cell.

3. The semiconductor memory cell array of claim 2 wherein the second region of the transistor of a memory cell of the third row of dynamic random access memory cells which is adjacent to a memory cell of the first row of dynamic random access memory cells is connected to the bit line associated with the adjacent memory cell.

4. The semiconductor memory cell array of claim 1 wherein memory cells of the first row of dynamic random access memory cells are written to simultaneously.

5. The semiconductor memory cell array of claim 1 wherein the semiconductor memory array is a portion of a logic device or a memory device.

6. The semiconductor memory cell array of claim 1 wherein one or more predetermined memory cells of the first row of dynamic random access memory cells are programmed to the second data state by programming each memory cell of the first row of dynamic random access memory cells to the first data state and thereafter programming the one or more predetermined memory cells of the first row of dynamic random access memory cells to the second data state.

7. An integrated circuit device, disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the integrated circuit device comprising:

a memory cell array having a plurality of memory cells arranged in a matrix of rows and columns, each memory cell includes at least one electrically floating body transistor having;

a first region, a second region, a body region disposed between the first region, the second region, and the insulating region or layer of the substrate, wherein the body region is electrically floating, and a gate spaced apart from the body region;

wherein, in response to control signals applied to a memory cell, the electrically floating body transistor associated therewith stores a charge which is representative of a data state of the memory cell in the body region of the electrically floating body transistor; and

wherein;

the first region of the transistor of each memory cell corresponding to a first row of memory cells is connected to a first source line,

the first region of the transistor of each memory cell corresponding to a second row of memory cells is connected to second source line, and

the first region of the transistor of each memory cell corresponding to a third row of memory cells is connected to a third source line;

wherein the first row of memory cells is adjacent to both the second and third rows of memory cells; and

wherein the second region of the transistor of each memory cell of the first row of memory cells shares the second region with the transistor of an adjacent memory cell of the second row of memory cells.

8. The integrated circuit device of claim 7 wherein:

the second region of the transistor of each memory cell of the first row of memory cells is connected to an associated bit line; and

the second region of the transistor of a memory cell of the second row of memory cells which is adjacent to a memory cell of the first row of memory cells is connected to the bit line associated with the adjacent memory cell.

9. The integrated circuit device of claim 8 wherein the second region of the transistor of a memory cell of the third row of memory cells which is adjacent to a memory cell of the first row of memory cells is connected to the bit line associated with the adjacent memory cell.

10. The integrated circuit device of claim 7 wherein memory cells of the first row of memory cells are written to simultaneously.

11. The integrated circuit device of claim 7 wherein:

the first region of the transistor of each memory cell corresponding to a fourth row of memory cells is connected to a fourth source line; and

the second region of the transistor of each memory cell of the third row of memory cells shares the second region with the transistor of an adjacent memory cell of the fourth row of memory cells.

12. The integrated circuit device of claim 7 wherein one or more predetermined memory cells of the first row of memory cells are programmed to the second data state by programming each memory cell of the first row of memory cells to the first data state and thereafter programming the one or more predetermined memory cells of the first row of memory cells to the second data state.

13. The integrated circuit device of claim 7 wherein each memory cell of the memory cell array consists essentially of the associated electrically floating body transistor.

14. An integrated circuit device, comprising:

a semiconductor memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, each memory cell consists essentially of an electrically floating body transistor, and wherein the electrically floating body transistor comprises;

a first region, a second region, a body region disposed between the first region and the second region, wherein the body region is electrically floating, and a gate spaced apart from the body region; and

wherein, in response to control signals applied to a memory cell, the electrically floating body transistor associated therewith stores a charge which is representative of a data state of the memory cell in the body region of the electrically floating body transistor; and

wherein;

the first region of the transistor of each memory cell corresponding to a first row of memory cells is connected to a first source line,

the first region of the transistor of each memory cell corresponding to a second row of memory cells is connected to second source line, and

the first region of the transistor of each memory cell corresponding to a third row of memory cells is connected to a third source line;

wherein the first row of memory cells is adjacent to both the second and third rows of memory cells; and

wherein the second region of the transistor of each memory cell of the first row of memory cells shares the second region with the transistor of an adjacent memory cell of the second row of memory cells.

15. The integrated circuit device of claim 14 wherein:

the second region of the transistor of each memory cell of the first row of memory cells is connected to an associated bit line; and

the second region of the transistor of a memory cell of the second row of memory cells which is adjacent to a memory cell of the first row of memory cells is connected to the bit line associated with the adjacent memory cell.

16. The integrated circuit device of claim 15 wherein the second region of the transistor of a memory cell of the third row of memory cells which is adjacent to a memory cell of the first row of memory cells is connected to the bit line associated with the adjacent memory cell.

17. The integrated circuit device of claim 14 wherein memory cells of the first row of memory cells are written to simultaneously.

18. The integrated circuit device of claim 14 wherein the semiconductor memory array is a portion of a logic device or a memory device.

19. The integrated circuit device of claim 14 wherein one or more predetermined memory cells of the first row of memory cells are programmed to the second data state by programming each memory cell of the first row of memory cells to the first data state and thereafter programming the one or more predetermined memory cells of the first row of memory cells to the second data state.

20. The integrated circuit device of claim 14 wherein each memory cell of the memory cell array consists of the associated electrically floating body transistor.