Mimicking program verify drain resistance in a memory device

• US 7,733,699 B2
• Filed: 06/24/2008
• Issued: 06/08/2010
• Est. Priority Date: 05/04/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US12/144,784
• Publication Number:
  US 20080259689A1
• Time in Patent Office: 714 Days
• Field of Search: 365/185.17, 365/185.18, 365/185.22
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A selected word line is biased with a program verify voltage. A predetermined quantity of unselected word lines that are between the selected word line and the bit line are biased with a modified V_pass voltage that is determined in response to a predetermined drain resistance. In one embodiment, the predetermined quantity is all of the word lines. Other embodiments can use smaller quantities. The remaining unselected word lines are biased with a normal V_pass voltage. The modified V_pass changes the resistance of the memory cells, acting as pass-gates during the program verification operation, to mimic a resistance of already programmed memory cells.

Claims

1. A method for programming a non-volatile memory device, the method comprising:

biasing a selected memory cell, in a series string of memory cells coupled between a source line and a bit line, with a program voltage;

biasing the selected memory cell with a program verify voltage during a verify operation; and

adjusting a drain resistance of the selected memory cell, during the verify operation, by biasing unselected memory cells of the series string of memory cells between the selected memory cell and a bit line with a modified V_pass voltage that produces an average drain resistance between the selected memory cell and the bit line that mimics a drain resistance of half of the unselected memory cells being programmed.

2. The method of claim 1 and further including biasing unselected memory cells between the selected memory cell and the source line with a V_pass voltage.

3. The method of claim 2 wherein the modified V_pass voltage is less than the V_pass voltage.

4. The method of claim 1 wherein the predetermined drain resistance is a predetermined resistance of a plurality of programmed memory cells acting as pass-gates.

5. The method of claim 1 wherein the selected memory cell is the memory cell adjacent to the source line and the unselected memory cells equal thirty-one memory cells.

6. The method of claim 1 wherein the modified V_pass voltage is a voltage that only partially turns on the unselected memory cells.

7. The method of claim 1 and further including repeating biasing the selected memory cell with the program voltage and the verify operation until the selected memory cell is programmed to a programmed logical state.

8. A method for programming a series string of memory cells in a non-volatile memory device, the method comprising:

biasing a selected memory cell of the series string with a programming voltage;

biasing the selected memory cell with a program verify voltage during a program verify operation; and

adjusting a drain resistance between the selected memory cell and a bit line of the series string, during the program verify operation, by biasing the unselected memory cells between the selected memory cell and the bit line with a modified V_pass voltage that changes in response to a quantity of memory cells remaining between the selected memory cell and the bit line as the selected memory cell moves upward from a source line of the series string towards the bit line.

9. The method of claim 8 wherein the modified V_pass voltage is changed in order to keep the drain resistance substantially constant as the selected memory cell moves from the source line to the bit line.

10. The method of claim 8 wherein an initial drain resistance is substantially equal to a drain resistance resulting from half the memory cells, between the selected memory cell and the bit line, being programmed.

11. The method of claim 10 wherein the initial drain resistance occurs when the selected memory cell is adjacent to the source line.

12. The method of claim 8 wherein biasing the selected memory cell comprises biasing the selected memory cell with a series of voltage pulses of incrementally increasing value prior to each program verify operation.

13. A method for programming a series string of non-volatile memory cells between a source line and a bit line, the method comprising:

biasing a selected memory cell with a program voltage wherein the selected memory cell begins adjacent to the source line and moves upward through the series string to be adjacent to the bit line; and

performing a program verify operation on the selected memory cell, after each program voltage, that comprises biasing the selected memory cell with a verify voltage and biasing a subgroup of unselected memory cells between the selected memory cell and the bit line with a modified V_pass voltage that is determined in response to a predetermined drain resistance wherein the subgroup of unselected memory cells is less than a number of memory cells between the selected memory cell and the bit line.

14. The method of claim 13 and further including biasing any remaining word lines not biased with the modified V_pass voltage and the verify voltage with a V_pass voltage that is greater than the modified V_pass.

15. The method of claim 14 wherein the series string of non-volatile memory cells are configured in a NAND architecture.

16. A NAND flash memory device comprising:

a memory array comprising a plurality of memory cell series string columns each coupled between a source line and a bit line; and

a memory control circuit coupled to the memory array and configured to generate a plurality of program pulses for biasing a selected memory cell, control a program verify operation between each program pulse wherein the program verify operation mimics an average drain resistance of a programmed quantity of memory cells between a selected memory cell and the bit line.

17. The memory device of claim 16 wherein the memory array is comprised of memory cells programmable as multilevel memory cells.

18. The memory device of claim 16 wherein the control circuit is further configured to generate a modified pass voltage that is determined in response to the average drain resistance, the control circuit further adapted to bias remaining unselected memory cells of the series string with a pass voltage that is greater than the modified pass voltage.

19. The memory device of claim 16 wherein the memory array is comprised of a plurality of flash memory cells.

20. The memory device of claim 16 wherein the average drain resistance is a resistance of the programmed quantity of memory cells acting as pass-gates during the program verify operation.