Storage subsystem with embedded circuit for protecting against anomalies in power signal from host

• US 7,733,712 B1
• Filed: 05/20/2008
• Issued: 06/08/2010
• Est. Priority Date: 05/20/2008
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: SiliconSystems, Inc. (Western Digital Corporation)
• Inventors: Diggs, Mark S., Walston, Wesley
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US12/123,932
• Time in Patent Office: 749 Days
• Field of Search: 365/189.11, 365/189.09, 365/226, 365/228, 365/229
• US Class Current: 365/189.11
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A storage subsystem includes a charge pump that receives a power signal from a host system, and generates a regulated power signal that is provided to the storage subsystem'"'"'s controller. When the power signal from the host is interrupted, the charge pump additionally acts as a backup power supply to enable the storage subsystem to continue to operate temporarily, and power isolation circuitry in the storage subsystem prevents power from flowing back to the host system. The storage subsystem further includes a digitally programmable voltage detection circuit that accepts various supply voltages and asserts a busy signal to the controller when an anomaly in the power signal is detected. The controller includes logic circuitry that will block the host system from performing write operations to the storage subsystem either when the voltage detection circuit asserts a busy signal or when the controller is busy executing memory operation commands.

Claims

1. A storage subsystem, comprising:

a controller that writes data to, and reads data from, a non-volatile storage medium;

a charge pump circuit that receives a power signal from a host system and generates a regulated power signal that is provided to the controller, wherein the charge pump circuit is capable of maintaining the regulated power signal to the controller when the power signal from the host system is interrupted;

an isolation circuit that substantially prevents power in the controller from flowing back to the host system when the power signal from the host system is interrupted, whereby the power is preserved in the controller to complete outstanding memory operations; and

a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, and responds to detection of such an anomaly by asserting a busy signal to the controller,

wherein the controller further comprises a ready/busy logic circuit that asserts a busy signal to block the host system from performing write operations to the storage subsystem when either or both of the following occur;

(a) the controller receives a busy signal from the voltage detection circuit;

(b) a busy signal is generated by the controller as a result of a memory access operation.

2. The storage subsystem of claim 1 wherein the charge pump circuit and the voltage detection circuit are integrated within a single application specific integrated circuit (ASIC).

3. The storage subsystem of claim 1 wherein the voltage detection circuit holds its output for a particular time period.

6. The storage subsystem of claim 1 wherein the isolation circuit further comprises a FET.

11. The storage subsystem as of claim 1, wherein the busy signal is provided on a ready/busy signal line used to inform the host system of whether the storage subsystem is ready to receive a next command.

12. The storage subsystem of claim 1, wherein ready/busy logic of the ready/busy circuit is implemented in hardware.

13. The storage subsystem of claim 1, wherein ready/busy logic of the ready/busy circuit is implemented in software.

4. A storage subsystem, comprising:

a controller that writes data to, and reads data from, a non-volatile storage medium;

a charge pump circuit that receives a power signal from a host system and generates a regulated power signal that is provided to the controller, wherein the charge pump circuit is capable of maintaining the regulated power signal to the controller when the power signal from the host system is interrupted;

an isolation circuit that substantially prevents power in the controller from flowing back to the host system when the power signal from the host system is interrupted, whereby the power is preserved in the controller to complete outstanding memory operations, the isolation circuit comprising;

a low dropout regulator;

a voltage input connected to an input terminal and an enable terminal of the low dropout regulator; and

at least one input capacitor connected between the voltage input and ground; and

a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, and responds to detection of such an anomaly by asserting a busy signal to the controller.

5. The storage subsystem of claim 4 wherein the isolation circuit further comprises:

a voltage output connected to an output terminal of the low dropout regulator;

a reference bypass capacitor connected to a reference bypass terminal of the low dropout regulator; and

at least one output capacitor connected between the voltage output and ground.

7. A storage subsystem, comprising:

a controller that writes data to, and reads data from, a non-volatile storage medium;

a charge pump circuit that receives a power signal from a host system and generates a regulated power signal that is provided to the controller, wherein the charge pump circuit is capable of maintaining the regulated power signal to the controller when the power signal from the host system is interrupted;

an isolation circuit that substantially prevents power in the controller from flowing back to the host system when the power signal from the host system is interrupted, whereby the power is preserved in the controller to complete outstanding memory operations; and

a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, and responds to detection of such an anomaly by asserting a busy signal to the controller,

wherein the isolation circuit comprises an opt-isolator.

8. A storage subsystem, comprising:

a controller that writes data to, and reads data from, a non-volatile storage medium;

a charge pump circuit that receives a power signal from a host system and generates a regulated power signal that is provided to the controller, wherein the charge pump circuit is capable of maintaining the regulated power signal to the controller when the power signal from the host system is interrupted;

an isolation circuit that substantially prevents power in the controller from flowing back to the host system when the power signal from the host system is interrupted, whereby the power is preserved in the controller to complete outstanding memory operations; and

a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, and responds to detection of such an anomaly by asserting a busy signal to the controller, the voltage detection circuit comprising;

a voltage detector;

a voltage input;

a voltage divider comprising at least one resistor, wherein the voltage divider is located between the voltage input and the voltage detector;

a input capacitor connected across the voltage input and to the voltage detector and ground; and

at least one resistor connected between the voltage detector and a voltage output.

9. The storage subsystem of claim 8 wherein the voltage divider comprises a digitally controlled potentiometer.

10. The storage subsystem of claim 9 wherein the digitally controlled potentiometer is controlled by the controller, wherein the controller is configured to adjust the digitally controlled potentiometer according to a supply voltage used by the host system.

14. A memory subsystem that protects against data losses caused by power signal anomalies, the memory subsystem comprising:

a solid state non-volatile memory array;

a controller that transfers data between a host system and the solid state non-volatile memory array, the controller comprising a logic unit;

a regulation circuit that receives a power signal from the host system, and generates a regulated power signal that is provided to the controller;

an isolation circuit that substantially prevents power in the controller from flowing back to the host system in the event of an anomaly in the power signal, whereby the power is preserved in the controller to complete outstanding memory operations; and

a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, wherein the voltage detection circuit responds to detection of the anomaly in the power signal by causing a busy signal to be asserted to the logic unit of the controller, wherein the busy signal asserted to the logic unit causes the controller to assert a busy signal to the host system to block the host system from performing write operations to the memory subsystem during presence of the anomaly.

15. The memory subsystem of claim 14, wherein the isolation circuit further comprises a low dropout regulator.

16. The memory subsystem of claim 14, wherein the isolation circuit further comprises a FET.

17. A memory subsystem that protects against data losses caused by power signal anomalies, the memory subsystem comprising:

a solid state non-volatile memory array;

a controller that transfers data between a host system and the solid state non-volatile volatile memory array, the controller comprising a logic unit;

a regulation circuit that receives a power signal from the host system, and generates a regulated power signal that is provided to the controller;

an isolation circuit that substantially prevents power in the controller from flowing back to the host system in the event of an anomaly in the power signal, whereby the power is preserved in the controller to complete outstanding memory operations; and

a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, wherein the voltage detection circuit responds to detection of the anomaly in the power signal by causing a busy signal to be asserted to the logic unit of the controller,

wherein the isolation circuit comprises an opt-isolator.

18. A memory subsystem that protects against data losses caused by power signal anomalies, the memory subsystem comprising:

a solid state non-volatile memory array;

a controller that transfers data between a host system and the solid state non-volatile volatile memory array, the controller comprising a logic unit;

a regulation circuit that receives a power signal from the host system, and generates a regulated power signal that is provided to the controller;

an isolation circuit that substantially prevents power in the controller from flowing back to the host system in the event of an anomaly in the power signal, whereby the power is preserved in the controller to complete outstanding memory operations; and

a voltage detection circuit that monitors the power signal from the host system to detect anomalies therein, wherein the voltage detection circuit responds to detection of the anomaly in the power signal by causing a busy signal to be asserted to the logic unit of the controller, the voltage detection circuit comprising a voltage divider.

19. The memory subsystem of claim 18 wherein the voltage divider comprises a digitally controlled potentiometer controlled by the controller, wherein the controller is configured to adjust the digitally controlled potentiometer according to a supply voltage used by the host system.

20. A method of responding to anomalies in a power signal provided by a host system to a storage subsystem, the method comprising, with the storage subsystem:

receiving the power signal from the host system, the host system being separate from the storage subsystem and pluggably connecting to the storage subsystem;

detecting an anomaly in the power signal with a detection circuit of the storage subsystem;

in response to detection of the anomaly by the detection circuit, asserting a signal to a controller of the storage subsystem to cause the controller to forward a signal to the host system to inhibit the host system from writing data to the storage subsystem during presence of the anomaly; and

during the presence of the anomaly, substantially preventing power from being drained from the storage subsystem toward the host system with a power isolation circuit, whereby the power is preserved on the storage subsystem to complete outstanding memory operations.

21. The method of claim 20, wherein the storage subsystem is a solid state non-volatile memory card.

22. The method of claim 20, wherein the storage subsystem is a disk drive.

23. The method of claim 20, wherein the signal is a busy signal used to notify the host system that the storage subsystem is currently in a busy state.

24. The method of claim 20, wherein the signal is provided to the host system on a ready/busy signal line of a standard card interface that interconnects the host system and the storage subsystem.

25. The method of claim 20, wherein the signal is generated by a logic circuit in the controller that generates the signal when either or both of the following occur:

(a) an anomaly is detected by the detection circuit;

(b) a busy signal is generated by a controller of the storage subsystem.

26. The method of claim 20, wherein the anomaly is a termination of power from the host system.

27. The method of claim 26, wherein the method further comprises the storage subsystem responding to the termination of power by using at least one source of backup power of the storage subsystem to perform a shut down sequence.

28. The method of claim 20, wherein, by asserting the signal to the host system, the storage subsystem additionally inhibits the host system from reading data from the storage subsystem.