Programmable pre-emphasis circuit for serial ATA

• US 7,733,920 B1
• Filed: 09/28/2007
• Issued: 06/08/2010
• Est. Priority Date: 10/22/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Hu, Timothy, Wu, Lei
• Primary Examiner(s): Phunkulh; Bob A
• Application Number:
  US11/904,886
• Time in Patent Office: 984 Days
• Field of Search: None
• US Class Current: 370/534
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03025 using a two-tap delay line

Abstract

A high-speed serial ATA physical layer includes a serial ATA control circuit. A serial ATA multiplexer outputs one of a plurality of serial ATA signals that is selected by the serial ATA control circuit. A serial ATA analog front end provides a first gain and pre-emphasis to the selected one of the plurality of serial ATA signals. The pre-emphasis alters a transmission characteristic of the selected one of the plurality of serial ATA signals.

Claims

1. A high-speed serial ATA physical layer comprising:

a serial ATA control circuit;

a serial ATA multiplexer that outputs one of a plurality of serial ATA signals,

wherein said one of said plurality of serial ATA signals is selected by said serial ATA control circuit; and

a serial ATA analog front end that provides a first gain and pre-emphasis to said selected one of said plurality of serial ATA signals,

wherein said pre-emphasis alters a transmission characteristic of said selected one of said plurality of serial ATA signals.

2. The high-speed serial ATA physical layer of claim 1, wherein said serial ATA physical layer is implemented in at least one of a serial ATA device and a serial ATA host.

3. The high-speed serial ATA physical layer of claim 1, wherein said multiplexer receives L input lines at x frequency and outputs said selected one of said plurality of serial ATA signals at L*x frequency, and wherein L*x is greater than 1.4 GHz.

4. The high-speed serial ATA physical layer of claim 1, wherein:

said communications channel has a band-limiting transmission characteristic; and

said pre-emphasis circuit compensates for said band-limiting transmission characteristic.

5. The high-speed serial ATA physical layer of claim 1, wherein said pre-emphasis is programmable.

6. The high-speed serial ATA physical layer of claim 5, wherein said serial ATA analog front end includes a pre-emphasis circuit that is programmed using at least one of data stored in memory and data input to said serial ATA physical layer.

7. The high-speed serial ATA physical layer of claim 1, wherein:

said serial ATA analog front end includes a pre-emphasis circuit; and

said pre-emphasis circuit compensates for transmission characteristics of the communications medium.

8. The high-speed serial ATA physical layer of claim 1, wherein said serial ATA pre-emphasis circuit adjusts gain of delayed signals that are generated based on said serial ATA signal to alter a transmission characteristic of said serial ATA signal.

9. The high-speed serial ATA physical layer of claim 1, wherein serial ATA pre-emphasis circuit provides said pre-emphasis based on a channel transmission characteristic.

10. The high-speed serial ATA physical layer of claim 1, wherein said pre-emphasis is preprogrammed.

11. A high-speed serial ATA physical layer comprising:

a serial ATA control circuit;

a serial ATA multiplexer that outputs one of a plurality of serial ATA signals,

wherein said one of said plurality of serial ATA signals that is selected by said serial ATA control circuit; and

a serial ATA analog front end that provides a first gain and pre-emphasis to said selected one of said plurality of serial ATA signals,

wherein;

said pre-emphasis alters a transmission characteristic of said selected one of said plurality of serial ATA signals; and

said serial ATA analog front end includes;

a first driver that generates a first amplified signal; and

a pre-emphasis circuit that includes;

a first delay element that delays said selected one of said plurality of serial ATA signals to generate a first delayed signal;

a second driver that amplifies said first delayed signal using a second gain to generate a second amplified signal; and

a first summing circuit that adds said first amplified signal and said second amplified signal to generate a sum.

12. The high-speed serial ATA physical layer of claim 11, wherein said pre-emphasis circuit further includes:

a second delay element that delays said second amplified signal to generate a second delayed signal; and

a third driver that amplifies said second delayed signal using a third gain to generate a third amplified signal,

wherein said first summing circuit adds said third amplified signal to said sum.

13. The high-speed serial ATA physical layer of claim 12, wherein said pre-emphasis circuit further includes:

a third delay element that delays said third amplified signal to generate a third delayed signal; and

a fourth driver that amplifies said third delayed signal using a fourth gain to generate a fourth amplified signal,

wherein said first summing circuit adds said fourth amplified signal to said sum.

14. The high-speed serial ATA physical layer of claim 13, wherein said first, second and third delay elements provide at least one of a unit delay and a partial unit delay.

15. The high-speed serial ATA physical layer of claim 11, wherein said second driver includes:

a pre-emphasis gain control circuit that controls said second gain; and

m differential amplifiers comprising;

differential inputs that communicate with first and second inputs;

differential outputs that communicate with first and second outputs and

enable inputs that communicate with said pre-emphasis gain control circuit,

wherein said pre-emphasis gain control circuit selectively enables said m differential amplifiers to adjust said second gain.

16. The high-speed serial ATA physical layer of claim 11, wherein said pre-emphasis circuit adjusts delays of said first and second delay elements based on the communication channel medium.

17. The high-speed serial ATA physical layer of claim 11, wherein said pre-emphasis circuit adjusts said first and second gains based on the communication channel medium.

18. A high-speed serial ATA physical layer comprising:

a serial ATA control circuit;

a serial ATA multiplexer that outputs one of a plurality of serial ATA signals,

wherein said one of said plurality of serial ATA signals that is selected by said serial ATA control circuit; and

a serial ATA analog front end that provides a first gain and pre-emphasis to said selected one of said plurality of serial ATA signals,

wherein;

said pre-emphasis alters a transmission characteristic of said selected one of said plurality of serial ATA signals; and

said serial ATA analog front end includes a first driver that includes;

a gain control circuit that controls said first gain; and

n differential amplifiers comprising;

differential inputs that communicate with first and second inputs;

differential outputs that communicate with first and second outputs; and

enable inputs that communicate with said gain control circuit,

wherein said gain control circuit selectively enables said n differential amplifiers to adjust said first gain.