Clock and data recovery circuits

• US 7,734,000 B2
• Filed: 05/02/2005
• Issued: 06/08/2010
• Est. Priority Date: 12/28/2004
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Kuo, Chun-Cheng, Huang, Li-Ren
• Primary Examiner(s): Liu; Shuwang
• Assistant Examiner(s): Perez; James M
• Application Number:
  US11/118,323
• Publication Number:
  US 20060140309A1
• Time in Patent Office: 1,863 Days
• Field of Search: 331/17, 375/354, 375360-362, 375/371, 375/373, 375375-376, 713/500, 713/50
• US Class Current: 375/375
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A clock and data recovery circuit comprising a phase detection circuit, first and second oscillators, and a flip-flop. The phase detection circuit outputs a detection signal according to a significant transition of an input signal. Each oscillator receives the detection signal and operates alternately in a clock and data recovery mode and a phase-locked mode. When the first oscillator operates in the clock and data recovery mode and outputs a first clock to control the flip-flop to output an output signal, the second oscillator operates in the phase-locked mode to adjust a frequency of a second clock. Before switching to the clock and data recovery mode, the second oscillator synchronizes the second clock with the first clock.

Claims

1. A clock and data recovery circuit receiving an input signal and outputting an output signal in phase with the input signal, comprising:

a phase detection circuit estimating a significant transition of the input signal and outputting a first detection signal;

a first oscillator receiving the first detection signal and outputting a first clock, wherein the first oscillator operates in a first mode during a first period and sequentially in second and synchronization modes during a second period;

a second oscillator receiving the first detection signal and outputting a second clock, wherein the second oscillator operates sequentially in the second and synchronization modes during the first period and operates in the first mode during the second period; and

a flip-flop receiving the input signal and outputting the output signal according to the first and second clocks respectively during the first and second periods,

wherein the first oscillator comprises;

a first multiplexer receiving the first clock and the first detection signal and controlled by a first select signal;

a first delay unit coupled to an output terminal of the first multiplexer;

a second multiplexer receiving the second clock and a signal output from the first delay unit and controlled by a second select signal; and

a second delay unit coupled to an output terminal of the second multiplexer and outputting the first clock,

wherein when the first oscillator operates in the first mode, the first multiplexer transmits the first clock to the first delay unit according to the first select signal at a first level or transmits the first detection signal to the first delay unit according to the first select signal at a second level; and

wherein when the first oscillator operates in the first mode, the second multiplexer transmits the signal output from the first delay unit to the second delay according to the second select signal.

2. The clock and data recovery circuit as claimed in claim 1, wherein during a third period, the first oscillator operates in the first mode.

3. The clock and data recovery circuit as claimed in claim 1, wherein during a third period, the second oscillator operates sequentially in the second and synchronization modes.

4. The clock and data recovery circuit as claimed in claim 1,

wherein during the first period, the first oscillator operates in the first mode and outputs the first clock to control the flip-flop to output the output signal;

and

wherein during the first period, the second oscillator operates in the second mode to adjust a frequency of the second clock and then operates in the synchronization mode to synchronize the second clock with the first clock.

5. The clock and data recovery circuit as claimed in claim 1,

wherein during the second period, the first oscillator operates in the second mode to adjust a frequency of the first clock and then operates in the synchronization mode to synchronize the first clock with the second clock;

and

wherein during the second period, the second oscillator operates in the first mode and outputs the second clock to control the flip-flop to output the output signal.

6. The clock and data recovery circuit as claimed in claim 1 further comprising

a frequency control circuit receiving a reference clock;

wherein during the first period, the frequency control circuit receives the second clock and generates a second control voltage to the second oscillator to adjust the frequency of the second clock; and

wherein during the second period, the frequency control circuit receives the first clock and generates a first control voltage to the first oscillator to adjust the frequency of the first clock.

7. The clock and data recovery circuit as claimed in claim 6 further comprising

a multiplexer receiving the first and second clocks and controlled by a first select signal;

wherein during the first period, the multiplexer outputs the first clock to the flip-flop and the second clock to the frequency control circuit according to the first select signal; and

wherein during the second period, the multiplexer outputs the second clock to the flip-flop and the first clock to the frequency control circuit according to the first select signal.

8. The clock and data recovery circuit as claimed in claim 6, wherein the frequency control comprises:

a frequency divider dividing the frequency of the second clock during the first period and the frequency of the first clock during the second period;

a phase/frequency detector receiving the reference clock, outputting a control signal according to the difference between the reference clock and the second clock during the first period, and outputting the control signal according to the difference between the reference clock and the first clock during the second period;

a charge pump receiving the control signal, changing the second control voltage according to the control signal during the first period, and changing the first control voltage according to the control signal during the second period; and

a first filter providing the first control voltage;

a second filter providing the second control voltage.

9. The clock and data recovery circuit as claimed in claim 8, wherein the frequency control circuit further comprises a de-multiplexer controlled by a first select signal, connecting the charge pump to the second filter during the first period, and connecting the charge pump to the first filter during the second period.

10. The clock and data recovery circuit as claimed in claim 1,

wherein when the first oscillator operates in the second mode, the first multiplexer transmits the first clock to the first delay unit according to the first select signal;

and

wherein when the first oscillator operates in the second mode, the second multiplexer transmits the signal output from the first delay unit to the second delay according to the second select signal.

11. The clock and data recovery circuit as claimed in claim 10,

wherein when the first oscillator operates in the synchronization mode, the first multiplexer transmits the first clock to the first delay unit according to the first select signal;

and

wherein when the first oscillator operates in the synchronization mode, the second multiplexer transmits the second clock to the second delay according to the second select signal.

12. The clock and data recovery circuit as claimed in claim 1 wherein the second oscillator comprises:

a third multiplexer receiving the second clock and the first detection signal and controlled by a third select signal;

a third delay unit coupled to an output terminal of the third multiplexer;

a fourth multiplexer receiving the first clock and a signal output from the third delay unit and controlled by a fourth select signal; and

a fourth delay unit coupled to an output terminal of the fourth multiplexer and outputting the second clock.

13. The clock and data recovery circuit as claimed in claim 12,

wherein when the second oscillator operates in the first mode, the third multiplexer transmits the second clock to the third delay unit according to the third select signal at a first level or transmits the first detection signal to the third delay unit according to the third select signal at a second level;

and

wherein when the second oscillator operates in the first mode, the fourth multiplexer transmits the signal output from the third delay unit to the fourth delay according to the fourth select signal.

14. The clock and data recovery circuit as claimed in claim 12,

wherein when the second oscillator operates in the second mode, the third multiplexer transmits the second clock to the third delay unit according to the third select signal;

and

wherein when the second oscillator operates in the second mode, the fourth multiplexer transmits the signal output from the third delay unit to the fourth delay according to the fourth select signal.

15. The clock and data recovery circuit as claimed in claim 12,

wherein when the second oscillator operates in the synchronization mode, the third multiplexer transmits the second clock to the third delay unit according to the third select signal;

and

wherein when the second oscillator operates in the synchronization mode, the fourth multiplexer transmits the first clock to the fourth delay according to the fourth select signal.

16. The clock and data recovery circuit as claimed in claim 12, wherein the phase detector further outputs a second detection signal delayed from the first detection signal.

17. The clock and data recovery circuit as claimed in claim 16, wherein the first oscillator further comprises:

a fifth multiplexer receiving the second detection signal and a first low level signal and controlled by a fifth select signal; and

a sixth multiplexer receiving a synchronizing signal and a second low level signal and controlled by a sixth select signal.

18. The clock and data recovery circuit as claimed in claim 17,

wherein when the first oscillator operates in the first mode, the fifth multiplexer selects the second detection signal to be the first select signal;

and

wherein when the first oscillator operates in the first mode, the sixth multiplexer selects the second low level signal to be the second select signal according to the sixth select signal.

19. The clock and data recovery circuit as claimed in claim 17,

wherein when the first oscillator operates in the second or synchronization mode, the fifth multiplexer selects the first low level signal to be the first select signal according to the fifth select signal;

and

wherein when the first oscillator operates in the second or synchronization mode, the sixth multiplexer selects synchronizing signal to be the second select signal according to the sixth select signal.

20. The clock and data recovery circuit as claimed in claim 19, wherein the synchronizing signal when the first oscillator operates in the second mode and the synchronizing signal when the first oscillator operates in the synchronization mode have different logic levels.

21. The clock and data recovery circuit as claimed in claim 17, wherein the first oscillator further comprises:

a seventh multiplexer receiving the second detection signal and the first low level signal and controlled by a seventh select signal; and

an eighth multiplexer receiving the synchronizing signal and the second low level signal and controlled by an eighth select signal.

22. The clock and data recovery circuit as claimed in claim 21,

wherein when the second oscillator operates in the first mode, the seventh multiplexer selects the second detection signal to be the seventh select signal;

and

wherein when the second oscillator operates in the first mode, the eighth multiplexer selects the second low level signal to be the fourth select signal according to the eighth select signal.

23. The clock and data recovery circuit as claimed in claim 21,

wherein when the second oscillator operates in the second or synchronization mode, the seventh multiplexer selects the first low level signal to be the third select signal according to the seventh select signal;

and

wherein when the second oscillator operates in the second or synchronization mode, the eighth multiplexer selects synchronizing signal to be the fourth select signal according to the eighth select signal.

24. The clock and data recovery circuit as claimed in claim 23, wherein the synchronizing signal when the second oscillator operates in the second mode and the synchronizing signal when the second oscillator operates in the synchronization mode have different logic levels.