Fractional frequency divider circuit and data transmission apparatus using the same

• US 7,734,001 B2
• Filed: 02/09/2005
• Issued: 06/08/2010
• Est. Priority Date: 02/09/2004
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Saeki, Takanori
• Primary Examiner(s): Payne; David C
• Assistant Examiner(s): NGUYEN, LEON VIET Q
• Application Number:
  US11/052,819
• Publication Number:
  US 20050174153A1
• Time in Patent Office: 1,945 Days
• Field of Search: 327/115, 327/117, 375/376, 377/116
• US Class Current: 375/376
• CPC Class Codes: H03K 23/546 with a base which is a non-integer
• CPC Class Codes: H03L 7/1974 for fractional frequency division

Abstract

A fractional frequency divider circuit with a small circuit scale that outputs a clock with a duty ratio of 50%, and a data transmission apparatus comprising same. The fractional frequency divider circuit is constituted by multiple master-slave flip-flops, and comprises an integer frequency divider circuit that frequency-divides a clock signal with a frequency-division ratio of 1/N(N is an integer), and a logic circuit into which multiple signals outputted from master stages and slave stages of the master-slave flip-flops are inputted and that outputs a signal with a duty ratio of 50% obtained by frequency-dividing the clock signal with a frequency-division ratio of 2/N. The data transmission apparatus is constituted such that it is possible to switch over between a frequency-multiplied clock outputted by a PLL and a clock obtained by frequency-dividing the frequency-multiplied clock with the fractional frequency divider circuit for each channel.

Claims

1. A fractional frequency divider circuit comprising:

an integer frequency divider circuit; and

a logic circuit,

wherein said integer frequency divider circuit comprises multiple master-slave flip-flops connected in series and each of the master flip-flops in the multiple master-slave flip-flops receives a first clock signal and each of the slave flip-flops in the multiple master slave flip-flops receives a clock signal which is 180 degrees out of phase with the first clock signal,

said integer frequency divider circuit frequency-divides the first clock signal with a frequency-division ratio of 1/N where N is an integer, and

said logic circuit receives a plurality of signals output from master stages and slave stages of said multiple master-slave flip-flops, and said logic circuit comprising a first data latch which receives a clock signal which is 90 degrees out of phase with the first clock signal and a second data latch which receives a clock signal which is 270 degrees out of phase with the first clock signal, and outputs a signal with a duty ratio of 50% obtained by frequency-dividing said first clock signal with a frequency-division ratio of 2/N.

2. The fractional frequency divider circuit as defined in claim 1 wherein said signals output from master stages or slave stages of said multiple master-slave flip-flops are supplied to said logic circuit, and

said fractional frequency divider circuit further comprises a data latch circuit that outputs an output signal synchronously with a clock signal whose waveform is the same as that of said first clock signal, but phase is different from that of said first clock signal.

3. A data transmission apparatus comprising:

a receiver circuit that performs serial-parallel conversion on a received signal and outputs the result;

a transmitter circuit that performs parallel-serial conversion on a transmitted signal and outputs the result;

a PLL that multiplies a reference clock signal and outputs a multiplied clock signal; and

a fractional frequency divider circuit that outputs a signal obtained by frequency-dividing said multiplied clock signal with a frequency-division ratio of 2/N where N is an integer,

wherein said fractional frequency divider circuit comprises an integer frequency divider circuit and a logic circuit, said integer frequency divider circuit comprising multiple master-slave flip flops connected in series and each of the master flip-flops in the multiple master-slave flip-flops receives a first clock signal and each of the slave flip-flops in the multiple master slave flip-flops receives a clock signal which is 180 degrees out of phase with the first clock signal,

said integer frequency divider circuit frequency-dividing said multiplied clock signal with a frequency-division ratio of 1/N,

said logic circuit receiving a plurality of signals output from master stages and slave stages of said multiple master-slave flip-flops, and said logic circuit comprising a first data latch which receives a clock signal which is 90 degrees out of phase with the multiplied clock signal and a second data latch which receives a clock signal which is 270 degrees out of phase with the multiplied clock signal, and outputting a signal obtained by frequency-dividing said multiplied clock signal with a frequency-division ratio of 2/N where N is an integer, and

said receiver circuit and transmitter circuit being constituted such that they operate selectively switching over between said multiplied clock signal and a clock signal output by said fractional frequency divider circuit.

4. The data transmission apparatus as defined in claim 3 wherein signals output from master stages or slave stages of said multiple master-slave flip-flops are supplied to said logic circuit,

said fractional frequency divider circuit further comprising a data latch circuit that outputs an output signal synchronously with a clock signal whose phase is different from said multiplied clock signal.

5. The data transmission apparatus as defined in claim 3 wherein the waveform of an output signal of said logic circuit has a duty ratio of 50%.

6. The data transmission apparatus as defined in claim 4 wherein the waveform of an output signal of said logic circuit has a duty ratio of 50%.

7. The data transmission apparatus as defined in claim 3 wherein said integer frequency divider circuit constitutes a frequency divider circuit that frequency-divides said multiplied clock signal and outputs the result to a phase comparator of said PLL.

8. The data transmission apparatus as defined in claim 4 wherein said integer frequency divider circuit constitutes a frequency divider circuit that frequency-divides said multiplied clock signal and outputs the result to a phase comparator of said PLL.

9. The data transmission apparatus as defined in claim 3 comprising multiple channels, wherein a pair of said receiver circuit and transmitter circuit forms one channel, and for each channel, selection is performed between said multiplied clock signal and a clock signal output by said fractional frequency divider circuit.

10. The data transmission apparatus as defined in claim 4 comprising multiple channels, wherein a pair of said receiver circuit and transmitter circuit forms one channel, and for each channel, selection is performed between said multiplied clock signal and a clock signal output by said fractional frequency divider circuit.

11. The data transmission apparatus as defined in claim 5 comprising multiple channels, wherein a pair of said receiver circuit and transmitter circuit forms one channel, and for each channel, selection is performed between said multiplied clock signal and a clock signal output by said fractional frequency divider circuit.

12. The data transmission apparatus as defined in claim 7 comprising multiple channels, wherein a pair of said receiver circuit and transmitter circuit forms one channel, and for each channel, selection is performed between said multiplied clock signal and a clock signal output by said fractional frequency divider circuit.