Memory with address-differentiated refresh rate to accommodate low-retention storage rows

• US 7,734,866 B2
• Filed: 08/04/2005
• Issued: 06/08/2010
• Est. Priority Date: 08/04/2005
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Tsern, Ely K.
• Primary Examiner(s): Shah; Sanjiv
• Assistant Examiner(s): Campos; Yaima
• Application Number:
  US11/198,708
• Publication Number:
  US 20070033338A1
• Time in Patent Office: 1,769 Days
• Field of Search: 711/100, 711/104, 711/105, 711/106, 711/108, 711113-114, 711/118, 365/185.25, 365/222
• US Class Current: 711/106
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50016 of retention

Abstract

In a dynamic random access memory device, receiving refresh commands via a signaling interface and, in response to the refresh commands, refreshing a first row of storage cells at a first refresh rate and refreshing a second row of storage cells at a second, faster refresh rate.

Claims

1. A memory controller comprising:

a first integrated circuit chip including

refresh control circuitry configured to generate a first-type refresh command at a first refresh rate by a first refresh address generator, and directed to a first row of storage cells within an external memory device at the first refresh rate and configured to generate a second-type refresh command at a second refresh rate by a second refresh address generator, and directed to a second row of storage cells within the external memory device at the second refresh rate,

wherein the second-type refresh command comprises an accelerated refresh rate which is higher than the first refresh rate; and

wherein the first row is one of a plurality of rows that exhibit at least a first retention time, and the second row of storage cells within the memory device exhibits a retention time that is shorter than the first retention time,

wherein the refresh control circuitry further comprises an address generating circuit configured to generate a series of repeating sequences of row addresses, each sequence of row addresses including a singular instance of a first address that corresponds to the first row of storage cells and plural instances of a second address that corresponds to the second row of storage cells, wherein, within a single sequence of the series of repeating sequences of row addresses, the singular instance of the first address may be located either before or after the location of any of the plural instances of the second address; and

output circuitry configured to output the first and second refresh command types to the external memory device according to the generated series of repeating sequences of row addresses, the external memory device comprising a second integrated circuit chip.

2. The memory controller of claim 1 wherein the address generating circuit comprises:

an address counter to generate a first sequence of addresses that includes a single instance of the first addresses and a single instance of the second address; and

an address insertion circuit to insert an additional instance of the second address between successive addresses of the first sequence in response to detecting that the first sequence of addresses has progressed to an address having a predetermined offset from the second address.

3. The memory controller of claim 1 wherein the first-type refresh command and the second-type refresh command are different commands and contain respective refresh rate indicia that, when received by the external memory device, cause the application of different internal refresh commands in the memory device.

4. The memory controller of claim 1 and further including circuitry to transfer data between the external memory device and a host in connection with a memory access operation.

5. A method of operation within a memory controller, the memory controller comprising a first integrated circuit chip, the method comprising:

generating a first number of first-type refresh commands at a first refresh rate by a first refresh address generator, and directed to a first row of storage cells within an external memory device at the first refresh rate,

the external memory device comprising a second integrated circuit chip;

generating a second, different number of second-type refresh commands at a second refresh rate by a second refresh address generator, and directed to a second row within the external memory device at the second refresh rate, the second refresh rate being faster than the first refresh rate;

wherein the first row is one of a plurality of rows that exhibit at least a first retention time, and the second row of storage cells within the memory device exhibits a retention time that is shorter than the first retention time;

algorithmically generating a series of repeating sequences of refresh addresses, in association with respective first-type refresh commands and second-type refresh commands, wherein, within a single sequence of refresh addresses, the addresses associated with the first-type refresh commands may be located either before or after the location of any of the addresses associated with the second-type refresh commands;

outputting the first and second refresh command types to the external memory device according to the generated series of repeating sequences of refresh addresses.

6. The method of claim 5 further comprising storing in a configuration circuit of the memory controller a value that specifies one of a plurality of algorithms for algorithmically generating the sequence of refresh addresses.

7. The method of claim 5 wherein generating the series of repeating sequences of refresh addresses comprises retrieving each refresh address in each sequence of refresh addresses from an address storage table of the memory controller.

8. The method of claim 7 further comprising loading the address storage table with the refresh addresses in an initialization operation.

9. A method of operation within a memory controller, the memory controller comprising a first integrated circuit chip, the method comprising:

generating first-type refresh commands at a first refresh rate by a first refresh address generator, directed to a first row of storage cells within an external memory device at the first rate, the external memory device comprising a second integrated circuit chip;

generating second-type refresh commands at a second refresh rate by a second fresh address generator, directed to a second row within the external memory device at the second rate, the second rate being faster than the first rate;

wherein the first row is one of a plurality of rows that exhibit at least a first retention time, and the second row of storage cells within the memory device exhibits a retention time that is shorter than the first retention time;

generating a series of repeating sequences of row addresses, each sequence of row addresses including a singular instance of a first address that corresponds to the first row and plural instances of a second address that corresponds to the second row, wherein, within a single sequence of row addresses, the singular instance of the first address may be located either before or after the location of any of the plural instances of the second address; and

outputting the first and second refresh command types to the external memory device according to the generated series of repeating sequences of row addresses.

10. The method of claim 9 wherein generating refresh commands directed to a first row comprises generating commands of a first-type and wherein generating refresh commands directed to a second row comprises generating commands of a second-type, the first-type and second-type commands being different and including indicia that, when received by the external memory device, cause the application of different internal refresh commands in the memory device.

11. The method of claim 9 and further including transferring data between the external memory device and a host in connection with a memory access operation.

12. A memory system comprising:

a first integrated circuit chip including a memory device having first and second rows of storage cells;

a second integrated circuit chip including a memory controller external to the memory device configured to issue first-type refresh commands at a first refresh rate by a first refresh address generator, to the memory device to effect the first refresh rate for the first row of storage cells and second-type refresh commands at a second, faster refresh rate, by a second refresh address generator for the second row of storage cells;

wherein the first row is one of a plurality of rows that exhibit at least a first retention time, and the second row of storage cells within the memory device exhibits a retention time that is shorter than the first retention time;

circuitry configured to generate a series of repeating sequences of row addresses, each sequence of row addresses including a singular instance of a first address that corresponds to the first row and plural instances of a second address that corresponds to the second row, wherein, within a single sequence of row addresses, the singular instance of the first address may be located either before or after the location of any of the plural instances of the second address;

non-volatile storage circuitry configured to store information indicative of an address of the second row, wherein the information indicative of an address of the second row comprises a value that indicates a pattern of addresses that includes the address of the second row; and

output circuitry configured to output the first and second refresh command types to the external memory device according to the generated series of repeating sequences of row addresses.

13. A method of operation within a memory system, the method comprising:

issuing first-type refresh commands at a first refresh rate by a first refresh address generator, from a first integrated circuit chip including a memory controller to a second integrated circuit chip including a memory device to effect the first refresh rate for a first row of storage cells within the memory device, the memory device disposed external to the memory controller;

retrieving information indicative of an address of a second row of storage cells from a non-volatile storage device, wherein the information indicative of an address of a second row of storage cells within the memory device comprises a value that indicates a pattern of addresses that includes the address of the second row;

issuing second-type refresh commands at a second refresh rate by a second refresh address generator to the memory device to effect the second refresh rate for the second row, the second refresh rate being faster than the first refresh rate;

wherein the first row is one of a plurality of rows that exhibit at least a first retention time, and the second row of storage cells within the memory device exhibits a retention time that is shorter than the first retention time;

generating a series of repeating sequences of row addresses, each sequence of row addresses including a singular instance of a first address that corresponds to the first row and plural instances of a second address that corresponds to the second row, wherein, within a single sequence of row addresses, the singular instance of the first address may be located either before or after the location of any of the plural instances of the second address; and

outputting the first and second refresh command types to the external memory device according to the generated series of repeating sequences of row addresses.

14. The method of claim 13 wherein issuing refresh commands comprises issuing refresh commands of a first-type and a second-type from the memory controller and having respective indicia that, when received by the external memory device, cause the application of different internal refresh commands in the memory device.

15. The method of claim 13 and further including transferring data between the external memory device and a host in connection with a memory access operation.

16. A method of operation within a memory system, the method comprising:

issuing first-type refresh commands at a first refresh rate by a first refresh address gene, from a first integrated circuit chip including a memory controller to a second integrated circuit chip including a memory device to effect the first refresh rate for a first row of storage cells within the memory device, the memory device disposed external to the memory controller, wherein the first row is one of a plurality of rows that exhibit at least a first retention time, and a second row of storage cells within the memory device exhibits a retention time that is shorter than the first retention time,

the method further comprising retrieving information indicative of a number of rows of storage cells within the memory device that exhibit a retention time that is shorter than the first retention time, and wherein issuing refresh commands to the memory device to effect the first refresh rate and issuing second-type refresh commands at a second refresh rate by a second refresh address generator, to the memory device to effect the second refresh rate collectively comprise issuing, during a refresh interval of the memory device, a number of refresh commands in accordance with the information indicative of the number of rows that exhibit the retention time that is shorter than the first retention time, the number of refresh commands exceeding the number of accessible rows of storage cells within the memory device;

generating a series of repeating sequences of refresh addresses within the memory device in response to the number of refresh commands, each sequence of refresh addresses including singular instances of addresses that correspond to the rows that exhibit at least the first retention time and plural instances of an address that corresponds to the second row, wherein, within a single sequence of refresh addresses, the addresses that correspond to the rows that exhibit at least the first retention time may be located either before or after the location of any of the plural instances of an address that corresponds to the second row; and

issuing the first and second refresh commands types to the memory device according to the generated series of repeating sequences of refresh addresses, to effect the second refresh rate for the second row of storage cells within the memory device, the second refresh rate being faster than the first refresh rate.

17. The method of claim 16 wherein issuing refresh commands to effect a first refresh rate comprises issuing commands of a first-type from the memory controller, and issuing refresh commands to effect a second refresh rate comprises issuing commands of a second-type from the memory controller, wherein the first-type and second-type commands are different and contain respective refresh rate indicia that, when received by the external memory device, cause the application of different internal refresh commands in the memory device.

18. The method of claim 16 wherein the memory controller includes circuitry to transfer data between the external memory device and a host in connection with a memory access operation.

19. A memory controller comprising:

a first integrated circuit chip including refresh control circuitry configured to generate a plurality of first-type refresh commands at a first refresh rate by a first refresh address generator, and directed to a plurality of normal retention rows of storage cells within a second integrated circuit chip including an external memory device at the first refresh rate and to generate a second-type refresh command at a second refresh rate by a second address generator, and directed to a low retention row of storage cells within the external memory device at the second refresh rate, the second refresh rate being faster than the first refresh rate,

wherein the low retention row exhibits a shorter retention time than the normal retention rows;

wherein the refresh control circuitry further comprises an address generating circuit configured to generate a series of repeating sequences of row addresses, each sequence of row addresses including singular instances of first addresses that correspond to the normal retention rows of storage cells and plural instances of a second address that corresponds to the low retention row of storage cells, and wherein, within a single sequence of refresh addresses, the singular instances of first addresses may be located either before or after the location of any of the plural instances of the second address; and

output circuitry configured to output the first and second refresh commands according to the generated series of repeating sequences of row addresses to the memory device.

20. The memory controller of claim 19 wherein the first refresh commands associated with a first refresh rate are different from the second refresh command associated with a second refresh rate, and wherein the first and second refresh commands, when received by the external memory device, cause application of different internal refresh commands in the memory device.

21. The memory controller of claim 19 and further including circuitry to transfer data between the external memory device and a host in connection with a memory access operation.

22. An integrated circuit memory chip configured to receive refresh commands of first-type, at a first refresh rate by a first refresh address generator, and refresh commands of a second type from a memory controller integrated circuit chip disposed on an external signaling path, wherein the refresh commands of first and second types are each signaled by respective particular combinations of command codes, the integrated circuit memory chip comprising:

first refresh circuitry configured to output first refresh addresses, directed to normal retention rows of storage cells within the memory chip, in response to refresh commands of the first type;

second refresh circuitry configured to output second refresh addresses, directed to low retention rows of storage cells within the memory chip, in response to refresh commands of the second type;

wherein the second-type refresh command comprises an accelerated refresh rate which is higher than the first refresh rate; and

wherein the low retention rows exhibit a shorter retention time than the normal retention rows;

address sequencing circuitry configured to generate a series of repeating sequences of row addresses, each sequence of row addresses including singular instances of the first refresh addresses and plural instances of the second refresh addresses, wherein, within a single sequence of row addresses, the singular instances of the first refresh addresses may be located either before or after the location of any of the plural instances of the second refresh addresses; and

output circuitry configured to output the first and second refresh command types to the external memory device according to the generated series of repeating sequences of row addresses.

23. A memory system comprising:

a memory module having a plurality of DRAM integrated circuit chips disposed thereon;

a memory controller comprising a controller integrated circuit chip external to the memory module configured to generate a plurality of first-type refresh commands at a first refresh rate by a first refresh address generator, and directed to a plurality of normal retention rows of storage cells within one of the plurality of DRAM integrated circuit chips at the first rate and configured to generate a second-type refresh command at a second refresh rate by a second refresh address generator, directed to a low retention row of storage cells within one of the plurality of DRAM integrated circuit chips at the second refresh rate, the second refresh rate being faster than the first refresh rate;

wherein the low retention row exhibits a shorter retention time than the normal retention rows;

the memory controller further comprising address generating circuitry configured to generate a series of repeating sequences of row addresses, each sequence of row addresses including singular instances of first addresses that correspond to the normal retention rows of storage cells and plural instances of a second address that corresponds to the low retention row of storage cells, wherein, within a single sequence of refresh addresses, the singular instances of first addresses may be located either before or after the location of any of the plural instances of the second address; and

output circuitry configured to output the first and second refresh commands according to the generated series of repeating sequences of row addresses to the plurality of DRAM integrated circuit chips.