Low power display refresh

• US 7,734,943 B2
• Filed: 04/03/2003
• Issued: 06/08/2010
• Est. Priority Date: 04/03/2003
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Intel Corporation
• Inventors: Whelan, Rochelle J., Grindstaff, Marcus
• Primary Examiner(s): Lee; Thomas
• Assistant Examiner(s): Yanchus, III; Paul B
• Application Number:
  US10/407,758
• Publication Number:
  US 20040199798A1
• Time in Patent Office: 2,623 Days
• Field of Search: 713300-375
• US Class Current: 713/324
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time
• CPC Class Codes: G09G 2360/127 Updating a frame memory using a transfer of data from a source area to a destination area
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: H04W 52/027 by controlling a display operation or backlight unit
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

An application processor coupled to a Static Random Access Memory (SRAM) interfaces with a graphics accelerator. A Dynamic Random Access Memory (DRAM) stores frame buffer data that may be transferred to a display through a switch located on the graphics accelerator in normal operation. In a power savings mode, the DRAM may be powered down and a copied frame buffer data stored in the SRAM may be transferred to the display through the switch.

Claims

1. A method comprising:

using a first display driver coupled to a graphics accelerator operating in a normal mode to supply frame buffer data from an external memory to a display;

copying the frame buffer data stored in the external memory to a memory embedded with a processor;

powering down the external memory and the first display driver in a power savings mode; and

refreshing the display using a second display driver to supply the copied frame buffer data stored in the memory embedded with the processor.

2. The method of claim 1, further comprising:

setting a switch in the graphics accelerator to change refreshing the display using the frame buffer data stored in the memory coupled to the graphics accelerator to using the copied frame buffer data stored in the memory coupled to the processor.

3. The method of claim 2 further comprising:

powering up the memory coupled to the graphics accelerator; and

setting the switch in the graphics accelerator to change refreshing the display using the copied frame buffer data stored in the memory coupled to the processor to using the frame buffer data stored in the memory coupled to the graphics accelerator.

4. The method of claim 1 wherein refreshing a display further comprises refreshing a Liquid Crystal Display (LCD).

5. The method of claim 1 wherein a memory coupled to the graphics accelerator includes coupling a Dynamic Random Access Memory (DRAM) to the graphics accelerator and a memory coupled to the processor includes coupling a Static Random Access Memory (SRAM) to the processor.

6. A method for displaying data, comprising:

fetching frame buffer data by a processor from a Dynamic Random Access Memory (DRAM) and a first display driver is used to provide a display with the fetched frame buffer data in normal operation;

copying the frame buffer data stored in the DRAM to an SRAM embedded with the processor; and

refreshing the display using a second display driver that receives the copied frame buffer data stored in the SRAM embedded with the processor.

7. The method of claim 6 further comprising:

copying the frame buffer data stored in the DRAM to the SRAM prior to operating in the power savings mode.

8. The method of claim 6 further comprising:

powering down the DRAM and the first display driver in the power savings mode.