Input control device and input control method

• US 7,734,983 B2
• Filed: 09/17/2004
• Issued: 06/08/2010
• Est. Priority Date: 09/25/2003
• Status: Expired due to Fees

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Li, Jifeng
• Primary Examiner(s): RIZK, SAMIR WADIE
• Application Number:
  US10/573,255
• Publication Number:
  US 20070022356A1
• Time in Patent Office: 2,090 Days
• Field of Search: 714/755, 714/786, 714/752, 714/804, 714/795, 714/751, 370/253
• US Class Current: 714/755
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding

Abstract

An input control apparatus capable of suppressing characteristic deterioration, reducing the circuit scale of a turbo decoder and effectively using memory of the turbo decoder. In this apparatus, control section (110) acquires information on a coding rate and coding block length of a received signal, determines the number of bits of systematic part Y1, and parity parts Y2 and Y3 in accordance with the coding rate and/or coding block length and so that the number of bits of one sequence of the parity parts falls below the number of bits of systematic part Y1 and controls bit number reduction section (109) so that the determined number of bits is obtained. Bit number reduction section (109) reduces the number of bits of systematic part Y1, and parity parts Y2 and Y3 output from separation section (108) under the control of control section (110) and decoder (111) performs turbo decoding using each sequence reduced by bit number reduction section (109).

Claims

1. An input control apparatus comprising:

a receiving section that receives a signal including bits of a systematic part and bits of parity parts comprising a plurality of sequences, the signal being generated in an external transmission apparatus by turbo coding and puncturing information;

a rate dematching processing section that performs rate dematching processing on the received signal; and

a bit number reduction section that discards bits from the systematic part and bits from the parity parts so that the number of bits in each sequence of the parity parts is less than the number of bits in the systematic part, at a timing between the rate dematching processing and turbo decoding on the signal subjected to the rate dematching processing.

2. An input control apparatus comprising:

a receiving section that receives a signal including bits of a systematic part and bits of parity parts compromising a plurality of sequences, the signal being generated in an external transmission apparatus by turbo coding and puncturing information;

a rate dematching processing section that performs rate dematching processing on the received signal; and

a bit number reduction section that discards bits from the systematic art and bits from the parity parts so that the number of bits in each sequence of the parity parts is less than the number of bits in the systematic part, before performing turbo decoding on the signal subjected to the rate dematching processing, wherein

the bit number reduction section discards the bits from the systematic part and the bits from the parity parts so that the number of bits in the parity parts is determined in accordance with a coding rate and/or coding block length of a bit sequence received as input in a turbo decoder.

3. The input control apparatus according to claim 2, wherein the bit number reduction section discards the bits from the systematic part and the bits from the parity parts so that the number of bits in the parity parts decreases as the coding rate of the bit sequence received as input in the turbo decoder decreases and the number of bits in the parity parts increases as the coding rate increases.

4. The input control apparatus according to claim 2, wherein the bit number reduction section discards the bits from the systematic part and the bits from the parity parts so that the number of bits in the parity parts decreases as the coding block length received as input in the turbo decoder increases and the number of bits in the parity parts increases as the coding block length decreases.

5. An input control method comprising the steps of:

receiving a signal including bits of a systematic part and bits of parity parts comprising a plurality of sequences, the signal being generated in an external transmission apparatus by turbo coding and puncturing information;

performing rate dematching processing on the received signal; and

discarding bits from the systematic part and bits from the parity parts so that the number of bits in each sequence of the parity parts is less than the number of bits in the systematic part, at a timing between the rate dematching processing and turbo decoding on the signal subjected to the rate dematching processing.

6. An input control method comprising the steps of:

receiving a signal including bits of a systematic part and bits of parity parts comprising a plurality of sequences, the signal being generated in an external transmission apparatus by turbo coding and puncturing information;

performing rate dematching processing on the received signal; and

discarding bits from the systematic part and bits from the parity parts so that the number of bits in each sequence of the parity parts is less than the number of bits in the systematic part, before performing turbo decoding on the signal subjected to the rate dematching processing, wherein

in the discarding, the bits from the systematic part and the bits from the parity parts are discarded so that the number of bits in the parity parts is determined in accordance with a coding rate and/or coding block length of a bit sequence received as input in a turbo decoder.