Automated circuit design dimension change responsive to low contrast condition determination in photomask phase pattern

• US 7,735,056 B2
• Filed: 03/30/2006
• Issued: 06/08/2010
• Est. Priority Date: 03/30/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Vickery, Carl Albert III, Palmer, Shane R., Aton, Thomas J.
• Primary Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US11/392,869
• Publication Number:
  US 20070231711A1
• Time in Patent Office: 1,531 Days
• Field of Search: 716/19, 716/21, 430/5
• US Class Current: 716/50
• CPC Class Codes: G03F 1/26 Phase shift masks [PSM]; PSM blanks; Preparation thereof
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging

Abstract

The present application is directed to methods of forming a phase pattern for an integrated circuit feature described in a design database as having a first target dimension. In one embodiment, the method comprises determining whether forming a phase pattern for the integrated circuit feature described in the design database will result in one or more phase blocks of the same phase type being positioned in relative proximity so as to result in a low contrast condition, selecting a second target dimension that will avoid the low contrast condition if the low contrast condition will result, and forming the phase pattern for an integrated circuit feature having the second target dimension. Systems for forming phase patterns and photomasks comprising the phase patterns of the present application are also disclosed.

Claims

1. A method of fabricating an integrated circuit using a photomask comprising a phase pattern for forming an integrated circuit feature described in a design database as having a first target dimension, the method comprising:

providing the photomask, including;

determining whether forming the integrated circuit using the photomask with a phase pattern for the integrated circuit feature having the first target dimension as described in the design database will result in one or more phase blocks of the same phase type being positioned in relative proximity to each other so as to result in a low contrast condition;

automatically changing the first target dimension to a second target dimension that will avoid the low contrast condition if the determining step determines that a low contrast condition will result; and

forming the phase pattern for the integrated circuit feature having the second target dimension; and

forming the integrated circuit with the integrated circuit feature having the second target dimension instead of the first target dimension using the photomask.

2. The method of claim 1, wherein selecting the second target dimension comprises choosing a second target dimension which is larger than the first target dimension by a pre-selected amount.

3. The method of claim 1, wherein forming the phase pattern further comprises:

generating a first phase pattern for the integrated circuit feature; and

correcting the first phase pattern to account for optical proximity effects to thereby form a corrected second phase pattern.

4. The method of claim 3, wherein changing the first target dimension to the second target dimension comprises choosing a second target dimension which is larger than the first target dimension by a pre-selected amount when forming the first phase pattern.

5. The method of claim 3, wherein providing the photomask further comprises generating one or more markers that identify the low contrast imaging condition in the first phase pattern.

6. The method of claim 5, wherein the process of changing the first target dimension to the second target dimension is carried out prior to generating the one or more markers, and further wherein the one or more markers are associated with the selected second target dimension.

7. The method of claim 5, wherein the process of changing the first target dimension to the second target dimension is carried out when forming the second phase pattern.

8. The method of claim 1, wherein the process of determining whether the low contrast condition will result comprises:

dividing the one or more phase blocks of the same phase type into a plurality of segments; and

determining whether the first target dimension of the integrated circuit feature is a non-critical dimension; and

, if so, determining whether a low contrast condition exists in which a segment is positioned in proximity to one or more other segments of the same phase type in a manner capable of causing low contrast imaging of a photoresist.

9. The method of claim 8, wherein the low contrast condition exists for a first segment if the first segment is within a pre-selected distance of one or more other segments of the same phase type.

10. The method of claim 8, wherein the low contrast condition exists for a first segment if a modeled light intensity between the first segment and one or more other segments of the same type is less than a pre-selected light intensity threshold.

11. The method of claim 8, wherein the low contrast condition exists for a first segment if a modeled light intensity between the first segment and one or more other segments of the same type is greater than a pre-selected light intensity threshold.

12. The method of claim 8, wherein, if the low contrast condition exists, changing the first target dimension to the second target dimension comprises increasing the target dimension of at least a portion of the integrated circuit feature associated with each segment for which the low contrast imaging condition exists.

13. The method of claim 1, wherein the determining process comprises determining whether forming a phase pattern for the integrated circuit feature described in the design database will result in a single phase block of the same phase type being positioned so that portions of the phase block are in relative proximity to each other so as to result in a low contrast condition.

14. The method of claim 1, wherein the determining process comprises determining whether forming the phase pattern for the integrated circuit feature described in the design database will result in two phase blocks of the same phase type being positioned in relative proximity to each other so as to result in a low contrast condition.

15. The method of claim 14, wherein the two phase blocks are both zero phase blocks.

16. The method of claim 14, wherein the two phase type are both π

phase blocks.

17. The method of claim 1, wherein the integrated circuit feature is an interconnect.

18. A method of claim 1, wherein the integrated circuit is formed using light transmitted through the photomask;

the first target dimension is less than about a wavelength of the light; and

the second target dimension is greater than the first target dimension.

19. A system for generating a phase pattern for a photomask, the system comprising:

a database operable to store data describing established design parameters of an integrated circuit to be fabricated with at least one integrated circuit feature having a first target dimension; and

a module coupled to the database, wherein the module comprises a set of instructions operable to;

determine whether forming the integrated circuit using a photomask with a phase pattern for the integrated circuit feature having the first target dimension as described in the database will result in one or more phase blocks of the same phase type being positioned in relative proximity to each other so as to result in a low contrast condition; and

generate some output to automatically alter the phase pattern to change the first target dimension in the established design parameters to a second target dimension for fabricating the integrated circuit that will avoid the low contrast condition if the low contrast condition will result.

20. The system of claim 19, wherein the module is operable to alter the phase pattern by increasing the size of the target dimension for the formed integrated circuit by a pre-selected amount so that the distance between the one or more phase blocks in the phase pattern is sufficient to avoid the low contrast condition.

21. The system of claim 20, wherein the module is operable to alter the phase pattern by generating one or more markers that identify the low contrast imaging condition in the phase pattern.

22. The system of claim 19, wherein the module is operable to determine whether the data describes a low contrast condition by:

dividing the one or more phase blocks into a plurality of segments; and

determining whether the first target dimension of the integrated circuit feature is a non-critical dimension, and if so, determining whether a low contrast condition exists in which a segment is positioned in proximity to one or more other segments of the same phase type in a manner capable of causing low contrast imaging of a portion of a photoresist mask used for patterning the integrated circuit feature.

23. The system of claim 22, wherein the module is operable to determine if the low contrast condition exists for a first segment by determining if the first segment is within a pre-selected distance of the one or more other segments of the same phase type.

24. The system of claim 22, wherein the module is operable to determine if the low contrast condition exists by determining if a modeled light intensity between the first segment and the one or more other segments of the same type is greater than a pre-selected light intensity threshold.

25. The system of claim 22, wherein the module is operable to determine if the low contrast condition exists by determining if a modeled light intensity between the first segment and the one or more other segments of the same type is less than a pre-selected light intensity threshold.

26. The system of claim 22, wherein if the low contrast condition exists, the module is capable of altering the phase pattern by increasing the target dimension of at least the portion of the integrated circuit feature associated with each segment for which the low contrast imaging condition exists.

27. The system of claim 19, wherein the module instructions describe the integrated circuit feature as an interconnect.