Lateral undercut of metal gate in SOI device

• US 7,736,956 B2
• Filed: 03/26/2008
• Issued: 06/15/2010
• Est. Priority Date: 08/17/2005
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doczy, Mark L., Dewey, Gilbert, Kavalieros, Jack, Doyle, Brian S., Brask, Justin K., Datta, Suman
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US12/079,587
• Publication Number:
  US 20080188041A1
• Time in Patent Office: 811 Days
• Field of Search: 438/151, 438/182, 438/691, 438/701, 438/713, 438/754
• US Class Current: 438/151
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.

Claims

1. A method for making a semiconductor device, comprising:

forming a gate dielectric on a second semiconductor layer on an insulator layer that is on a first semiconductor layer;

forming a metal gate electrode on the gate dielectric, the metal gate electrode having a first side and a second side;

removing portions of the metal gate electrode on the first side and the second side to form curved lateral undercuts extending into a center of the metal gates thickness and tapering off towards a top and a bottom surface of the metal gate said curved lateral undercuts having a depth laterally measured from an outermost edge of the metal gate to a greatest depth of the lateral undercut;

forming source/drain regions of the second semiconductor layer on the first and second side of the metal gate electrode, the source/drain regions having extensions a distance beneath the metal gate electrode; and

wherein the depth of the lateral undercuts are at least about one-fourth the distance of the source/drain region extensions.

2. The method of claim 1, wherein forming said gate dielectric and said metal gate electrode are formed by a metal comprising:

forming a layer of dielectric material on the second semiconductor layer;

forming a metal layer on the layer of dielectric material;

removing portions of the metal layer to leave behind the metal gate electrode; and

removing portions of the layer of dielectric material to leave behind the gate dielectric.

3. The method of claim 2, further comprising:

determining a desired threshold voltage for the semiconductor device;

determining a thickness of the metal gate electrode that results in the desired threshold voltage; and

wherein forming a metal layer on the layer of dielectric material comprises forming the metal layer with a thickness about equal to the thickness of the metal gate electrode that results in the desired threshold voltage.

4. The method of claim 2, wherein the layer of dielectric material comprises a high-k dielectric material and wherein the metal layer on the layer of dielectric material comprises a material selected from the group consisting of a p-type metal, an n-type metal, and a mid-gap metal.