Method of forming nanotube vertical field effect transistor

• US 7,736,979 B2
• Filed: 06/20/2007
• Issued: 06/15/2010
• Est. Priority Date: 06/20/2007
• Status: Expired due to Fees

• Current Assignee: New Jersey Institute of Technology
• Original Assignee: New Jersey Institute of Technology
• Inventors: Goyal, Amit, Farrow, Reginald Conway
• Primary Examiner(s): Pert; Evan
• Assistant Examiner(s): MUNOZ, ANDRES F
• Application Number:
  US11/765,788
• Publication Number:
  US 20080315302A1
• Time in Patent Office: 1,091 Days
• Field of Search: 977/902, 977932-938, 257/E39, 257E51038-E5104, 257/E23.074, 257/E23.165, 257/E39.013, 257/E29.322, 257/E49.003, 257/E21.404, 257/E21.408
• US Class Current: 438/270
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H10K 10/491 Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

A nanotube field effect transistor and a method of fabrication are disclosed. The method includes electrophoretic deposition of a nanotube to contact a region of a conductive layer defined by an aperture. Embodiments of the present disclosure provide a method of depositing nanotubes in a region defined by an aperture, with control over the number of nanotubes to be deposited, as well as the pattern and spacing of nanotubes. For example, electrophoretic deposition, along with proper configuration of the aperture, allows at least one nanotube to be deposited in a target region with nanometer scale precision. Pre-sorting of nanotubes, e.g., according to their geometries or other properties, may be used in conjunction with embodiments of the present disclosure to facilitate fabrication of devices with specific performance requirements.

Claims

1. A method of forming a nanotube field effect transistor (FET), comprising:

providing a multi-layer stack having materials in an order of;

a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer;

forming a first aperture in at least a top portion of the second insulating layer;

forming a second aperture in the second conductive layer and the first insulating layer to expose a region of the first conductive layer, the second aperture being centrally aligned with respect to the first aperture and having a diameter smaller than a diameter of the first aperture;

generating an electric field proximate to the first aperture, the electric field configured to direct a plurality of nanotubes towards the exposed region of the first conductive layer;

depositing a first nanotube on the exposed region of the first conductive layer by electrophoresis, with a first end of the first nanotube contacting the exposed region of the first conductive layer proximate a center of the exposed region of the first conductive layer;

wherein the first aperture and the second aperture are sized to allow the plurality of nanotubes to contact the exposed region of the first conductive layer; and

wherein after the first nanotube is deposited, the deposited first nanotube re-configures the electric field to thereby prevent other nanotubes from the plurality of nanotubes from being deposited on the exposed region of the first conductive layer.

2. The method of claim 1, wherein the first aperture exposes a region of the second conductive layer;

and

wherein the step of forming the second aperture includes the steps of;

(i) depositing a second nanotube on the exposed region of the second conductive layer by electrophoresis, with a first end of the second nanotube contacting the exposed region of the second conductive layer proximate a center of the exposed region of the second conductive layer;

(ii) depositing a dielectric material in the first aperture to substantially fill the first aperture with the dielectric material;

(iii) removing the second nanotube to form a third aperture in the substantially filled first aperture, the third aperture having a diameter substantially the same as the diameter of the removed second nanotube;

(iv) forming the second aperture in the second conductive layer and the first insulating layer to expose a region of the first conductive layer, the second aperture having a diameter substantially the same as the diameter of the third aperture; and

(v) substantially removing the dielectric material from the first aperture; and

wherein the first nanotube is a single-walled carbon nanotube, the second nanotube is a multi-walled carbon nanotube, and the plurality of nanotubes are single-walled carbon nanotubes.

3. The method of claim 1, wherein the first nanotube is a single-walled carbon nanotube.

4. The method of claim 1, wherein the electrophoresis comprises applying a bias voltage to the second conductive layer.

5. The method of claim 4, wherein the electrophoresis further comprises exposing the multi-layer stack to a suspension of nanotubes in a liquid bath containing an electrolyte, and applying the bias voltage between the second conductive layer and an electrode in the liquid bath.

6. The method of claim 1, wherein the first conductive layer forms one of a source or a drain of the FET, and the second conductive layer forms a gate of the FET.

7. The method of claim 1, further comprising:

providing a dielectric layer over a vertical sidewall of the second conductive layer inside the second aperture, the dielectric layer forming a gate dielectric of the FET.

8. The method of claim 1, further comprising:

providing a third conductive layer over the second insulating layer, the third conductive layer contacting one end of the first nanotube and forming one of a source or a drain of the FET.

9. The method of claim 1, wherein the first and second conductive layers are each provided as a part of two metallization mask levels of a complementary metal oxide semiconductor (CMOS), the CMOS and the FET being devices in one semiconductor structure.

10. A method of forming a nanotube field effect transistor (FET), comprising:

providing a structure having at least a top conductive layer over an insulating layer formed on a bottom conductive layer;

forming an aperture through the top conductive layer and the insulating layer to expose;

(i) a vertical sidewall of the top conductive layer and, (ii) a horizontal region of the bottom conductive layer, the aperture sized to allow a plurality of nanotubes to contact the exposed horizontal region of the bottom conductive layer;

forming a dielectric layer over the vertical sidewall of the top conductive layer;

generating an electric field proximate to the aperture, the electric field configured to direct the plurality of nanotubes towards the exposed horizontal region of the bottom conductive layer;

depositing a first nanotube on the exposed horizontal region of the bottom conductive layer by electrophoresis, with a first end of the first nanotube contacting the exposed horizontal region of the bottom conductive layer proximate a center of the horizontal region, and the deposited first nanotube re-configuring the electric field to thereby prevent other nanotubes from the plurality of nanotubes from being deposited on the exposed horizontal region of the bottom conductive layer; and

orienting the first nanotube to provide contact between an intermediate portion of the first nanotube and the dielectric layer.

11. The method of claim 10, wherein orienting the first nanotube is performed by applying a voltage across the top conductive layer and the bottom conductive layer.

12. The method of claim 10, wherein the bottom conductive layer forms one of a source or a drain of the FET, the top conductive layer forms a gate of the FET, the dielectric layer forms a gate dielectric of the FET, and the intermediate portion of the first nanotube forms a channel region of the FET.

13. A method of forming a semiconductor structure, comprising:

forming a horizontal field effect transistor (FET) on a substrate;

forming a vertical nanotube field effect transistor (NT-FET) over the horizontal FET;

wherein the vertical NT-FET is formed using a method comprising;

(a) providing a structure having at least a first insulating layer on a first conductive layer;

(b) forming a first aperture in the first insulating layer to expose a region of the first conductive layer;

(c) generating an electric field proximate to the first aperture, the electric field configured to direct a plurality of nanotubes towards the exposed region of the first conductive layer;

(d) depositing a nanotube on the exposed region of the first conductive layer by electrophoresis, the deposited nanotube having one end contacting the exposed region of the first conductive layer proximate a center of the exposed region;

wherein the first conductive layer forms one of a source or a drain of the NT-FET;

wherein the first aperture is sized to allow the plurality of nanotubes to contact the exposed region of the first conductive layer; and

wherein after the nanotube is deposited, the deposited nanotube re-configures the electric field to thereby prevent other nanotubes from the plurality of nanotubes from being deposited on the exposed region of the first conductive layer.

14. The method of claim 13, wherein the structure further comprises a second conductive layer formed on the first insulating layer, and a second insulating layer formed on the second conductive layer;

the method further comprising;

forming a second aperture in the second insulating layer, the second aperture having a diameter larger than a diameter of the first aperture and being centrally aligned with the first aperture;

performing electrophoresis by applying a bias voltage to the second conductive layer, while immersing the structure to a liquid bath containing a suspension of nanotubes.

15. A method of forming a plurality of nanotube field effect transistors;

comprising;

providing a first insulating layer over a first conductive layer;

forming an elongated aperture in the first insulating layer to expose a region of the first conductive layer, the aperture characterized by a width and a length larger than the width;

generating an electric field proximate to the aperture, the electric field configured to direct a first plurality of nanotubes to the exposed region of the first conductive layer;

depositing a second plurality of nanotubes in a line pattern on the exposed region of the first conductive layer by electrophoresis;

wherein the width of the aperture is sufficiently small to restrict deposition of the second plurality of nanotubes to the line pattern and the number of nanotubes in the second plurality of nanotubes is determined at least in part by the length of the aperture;

wherein the aperture is sized to allow the first plurality of nanotubes to contact the exposed region of the first conductive layer;

wherein after the second plurality of nanotubes is deposited, the deposited second plurality of nanotubes re-configures the electric field to thereby prevent other nanotubes from the first plurality of nanotubes from being deposited on the exposed region of the first conductive layer; and

wherein the number of nanotubes in the first plurality of nanotubes is greater than the number of nanotubes in the second plurality of nanotubes.