Blocking dielectric engineered charge trapping memory cell with high speed erase

• US 7,737,488 B2
• Filed: 08/27/2007
• Issued: 06/15/2010
• Est. Priority Date: 08/09/2007
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Liao, Chien Wei, Lai, Sheng Chih, Lue, Hang-Ting
• Primary Examiner(s): Jackson, Jr.; Jerome
• Assistant Examiner(s): Chen; Yu
• Application Number:
  US11/845,321
• Publication Number:
  US 20090039416A1
• Time in Patent Office: 1,023 Days
• Field of Search: 257/324, 257/325, 257/E21.423, 257/E29.309, 438/287
• US Class Current: 257/325
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

Claims

1. A charge trapping memory comprising an array of memory cells, respective memory cells in the array including:

a semiconductor body including a channel having a channel surface, and source and drain terminals adjacent the channel;

a dielectric stack between a gate and the channel surface;

the dielectric stack comprising;

a tunneling dielectric layer;

a charge trapping dielectric layer on the tunneling dielectric layer;

a blocking dielectric layer on the charge trapping dielectric layer, the blocking dielectric layer comprising a metal doped silicon oxide having a dielectric constant κ

between 4.5 and 7.

2. The memory of claim 1, wherein the blocking dielectric layer is on the channel surface.

3. The memory of claim 1, wherein the tunneling dielectric layer is on the channel surface, and an electron barrier height between the gate and the blocking dielectric layer is more than 3 eV.

4. The memory of claim 1, wherein the tunneling dielectric layer comprises a combination of materials arranged to establish a relatively low valence band energy level near the channel surface, and an increase in valence band energy level at a first offset from the channel surface and a decrease in valence band energy at a second offset more than 2 nm from the channel surface.

5. The memory of claim 1, including:

circuitry, coupled to the array of memory cells, to apply bias voltages to selected memory cells for read, program and erase operations, including bias voltages across the gate and semiconductor body to induce an electric field having a magnitude of less than 14 MV/cm to cause hole tunneling through the tunneling dielectric layer.

6. The memory of claim 1, wherein the metal in the metal doped silicon oxide comprises aluminum having a concentration between 0.1 and 50 atomic percent relative to a sum of aluminum and silicon atoms.

7. The memory of claim 1, wherein the tunneling dielectric layer is on the channel surface, and the gate comprises a metal, metal compound, n+ doped polysilicon or p+ doped polysilicon.

8. The memory of claim 1, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness less than 20 Å

, a low barrier height layer on the first silicon oxide layer, having a hole tunneling barrier height less than 3 eV, and an isolation layer isolating the low barrier height layer from the charge trapping dielectric layer.

9. The memory of claim 8, wherein the thickness of the first silicon oxide layer is 15 Å

or less.

10. The memory of claim 1, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness of 20 Å

or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 30 Å

or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å

or less.

11. The memory of claim 1, wherein the tunneling dielectric layer is on the channel surface, and the electron barrier height for the blocking layer is greater than 3 eV.

12. The memory of claim 1, wherein the tunneling dielectric layer is on the channel surface, and the electron barrier height for the blocking layer is greater than 3.2 eV and the dielectric constant is greater than 5.

13. A charge trapping memory comprising an array of memory cells, respective memory cells in the array including:

a semiconductor body including a channel having a channel surface, and source and drain terminals adjacent the channel;

a tunneling dielectric layer on the channel surface, including a first silicon oxide layer adjacent the channel and having a thickness of 20 Å

or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 30 Å

or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å

or less;

a charge trapping layer on the tunneling dielectric layer comprising silicon nitride having a thickness of 50 Å

or more;

a blocking dielectric layer on the charge trapping layer, the blocking dielectric layer comprising aluminum doped silicon oxide having between 0.1 and 50 atomic % aluminum relative to a sum of aluminum and silicon atoms; and

a gate on the blocking dielectric layer comprising polysilicon.

14. The memory of claim 13, wherein the dielectric constant of the blocking dielectric layer is greater than 5, and the gate comprises P+ polysilicon.

15. A method for manufacturing a charge trapping memory comprising:

forming a semiconductor body including a channel region on a semiconductor body, the channel region having a channel surface, and source and drain terminals adjacent the channel;

forming a gate overlying the channel region;

forming dielectric stack between the channel surface and the gate, including forming a tunneling dielectric layer;

forming a charge trapping dielectric layer; and

forming a blocking dielectric layer, the blocking dielectric layer comprising a metal doped silicon oxide having a dielectric constant κ

between 4.5 and 7.

16. The method of claim 15, wherein an electron barrier height between the gate and the blocking dielectric layer is more than 3 eV.

17. The method of claim 15, wherein the tunneling dielectric layer comprises a combination of materials arranged to establish a relatively low valence band energy level near the channel surface, and an increase in valence band energy level at a first offset from the channel surface and a decrease in valence band energy at a second offset more than 2 nm from the channel surface.

18. The method of claim 15, wherein the metal in the metal doped silicon oxide comprises aluminum having a concentration between 0.1 and 50 atomic percent relative to a sum of aluminum and silicon atoms.

19. The method of claim 15, wherein the gate comprises a metal, a metal compound, n+ doped polysilicon or p+ doped polysilicon.

20. The method of claim 15, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness less than 20 Å

, a low barrier height layer on the first silicon oxide layer, having a hole tunneling barrier height less than 3 eV, and an isolation layer isolating the low barrier height layer from the charge trapping dielectric layer.

21. The method of claim 20, wherein the thickness of the first silicon oxide layer is 15 Å

or less.

22. The method of claim 15, wherein the tunneling dielectric layer comprises a first silicon oxide layer adjacent the channel and having a thickness of 20 Å

or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 30 Å

or less, and a silicon oxide layer on the silicon nitride layer having a thickness of 30 Å

or less.

23. The method of claim 15, wherein the electron barrier height for the blocking layer is greater than 3 eV.

24. The method of claim 15, wherein the electron barrier height for the blocking layer is greater than 3.2 eV and the dielectric constant is greater than 5.