Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain

• US 7,737,502 B2
• Filed: 02/10/2006
• Issued: 06/15/2010
• Est. Priority Date: 06/09/2004
• Status: Active Grant

• Current Assignee: X Corp. (f/k/a Twitter, Inc.) (X Holdings Corp.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bronner, Gary B., Kim, Byeong Y., Divakaruni, Ramachandra, Beintner, Jochen
• Primary Examiner(s): Monbleau; Davienne
• Assistant Examiner(s): REAMES, MATTHEW L
• Application Number:
  US11/351,801
• Publication Number:
  US 20060128111A1
• Time in Patent Office: 1,586 Days
• Field of Search: 257/368, 257/397, 257/E29.018, 257/E23.013
• US Class Current: 257/366
• CPC Class Codes: H01L 21/76243 using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/516 with at least one ferroelectric layer
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: Y10S 438/938 Lattice strain control or utilization

Abstract

The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.

Claims

1. A strained Si/SGOI structure comprising:

an active device region comprising a relaxed SiGe layer present on a buried insulating layer, in which the buried insulating layer is continuously extending across an entire width of a semiconductor substrate, a strained Si layer is located atop the relaxed SiGe layer, wherein the sidewalls of the relaxed SiGe layer are recessed to provide a void at each sidewall of the relaxed SiGe layer that is not filled with any material, a raised source/drain region located atop a portion of said strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and

a raised trench oxide region surrounding said active device region, wherein an upper surface of the raised trench oxide region is raised above an upper surface of the raised source/drain region.

2. The strained Si/SGOI structure of claim 1 further comprising an oxide spacer abutting said stack.

3. The strained Si/SGOI structure of claim 1 wherein said raised source/drain region is separated from said stack and said raised trench oxide by nitride.

4. The strained Si/SGOI structure of claim 1 wherein said strained Si layer is in contact with said raised trench oxide region.

5. The strained Si/SGOI structure of claim 1 wherein said gate polySi includes two polySi layers.

6. The strained Si/SGOI structure of claim 1 wherein said gate dielectric is an oxide or an oxide containing nitrogen therein.

7. The strained Si/SGOI structure of claim 1 wherein said gate dielectric is a thermal SiO₂ layer.

8. The strained Si/SGOI structure of claim 1 wherein said relaxed SiGe layer is an upper layer of a SGOI substrate, which further includes the buried insulating layer, the buried insulating layer having said raised trench oxide region located thereon.

9. The strained structure of claim 1 wherein an oxide cap is present on said gate polySi.

10. A strained Si/SGOI structure comprising an active device region comprising a relaxed SiGe layer present on a buried insulating layer, in which the buried insulating layer is continuously extending across an entire width of a semiconductor substrate, a strained Si layer is located atop the relaxed SiGe layer, wherein the sidewalls of the relaxed SiGe layer are recessed to provide a void at each sidewall of the relaxed SiGe layer that is not filled with any material, a raised source/drain region located atop a portion of said strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer;

and

a raised trench oxide region surrounding said active device region, wherein an upper surface of the raised trench oxide region is raised above an upper surface of the raised source/drain region, in which the void is present between the relaxed SiGe layer and the raised trench oxide region.