Semiconductor device and method for fabricating the same

• US 7,737,510 B2
• Filed: 10/11/2006
• Issued: 06/15/2010
• Est. Priority Date: 10/27/2005
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Akamatsu, Susumu
• Primary Examiner(s): PRENTY, MARK V
• Application Number:
  US11/545,427
• Publication Number:
  US 20070096184A1
• Time in Patent Office: 1,343 Days
• Field of Search: 257/408, 257/369, 257/900, 257/903
• US Class Current: 257/408
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A gate insulating film and a gate electrode are formed on an active region of a semiconductor substrate. A sidewall forming an L shape in cross section is formed on the sides of the gate electrode. Source/drain regions are formed in regions of the semiconductor substrate located outside an area covering the gate electrode and the sidewall. A stress-applying stress liner film is formed to cover the gate electrode and the sidewall.

Claims

1. A semiconductor device having a MIS transistor, said MIS transistor comprising:

a first gate insulating film formed on a semiconductor substrate;

a first gate electrode formed on the first gate insulating film;

a first sidewall covering the sides of the first gate electrode and the top surface of part of the semiconductor substrate and made of a first insulating film forming an L shape in cross section;

first source/drain regions formed in regions of the semiconductor substrate located outside an area covered by the first gate electrode and the first sidewall;

a stress-applying insulating film covering the first gate electrode and the first sidewall; and

a second sidewall forming a plate-like shape in cross section and made of a second insulating film, the second sidewall being formed between the first gate electrode and the first sidewall, wherein

the stress-applying insulating film is in contact with the bend of the L-shaped first sidewall, and

a third sidewall forming an L shape in cross section and made of a third insulating film is formed between the first sidewall and the second sidewall and between the semiconductor substrate and the first sidewall.

2. The semiconductor device of claim 1, wherein

the semiconductor substrate is made of silicon, and

a gate length direction of the first gate electrode is along a <

100>

orientation of the silicon.

3. The semiconductor device of claim 1, wherein

silicide layers are formed in an upper portion of the first gate electrode and respective upper portions of the first source/drain regions.

4. The semiconductor device of claim 1, wherein

SD extension diffusion regions are formed in regions of the semiconductor substrate located under the first sidewall.

5. The semiconductor device of claim 1, wherein

the MIS transistor is an N-type MIS transistor, and

the stress-applying insulating film has a tensile stress.

6. The semiconductor device of claim 5 further comprising

a P-type MIS transistor,

wherein the P-type MIS transistor comprises:

a second gate insulating film formed on the semiconductor substrate;

a second gate electrode formed on the second gate insulating film;

a fourth sidewall formed on the sides of the second gate electrode, forming an L shape in cross section, and made of the first insulating film;

a fifth sidewall formed on the fourth sidewall and made of a fourth insulating film; and

second source/drain regions formed in regions of the semiconductor substrate located outside an area covered by the second gate electrode and the third sidewall.

7. The semiconductor device of claim 6 further comprising:

an interlayer dielectric covering the N-type MIS transistor and the P-type MIS transistor; and

a contact passing through the interlayer dielectric and reaching the second source/drain regions of the P-type MIS transistor,

wherein the contact comes into contact with the fifth sidewall.

8. The semiconductor device of claim 6, wherein

the N-type MIS transistor and the P-type MIS transistor form an SRAM.

9. The semiconductor device of claim 1, wherein

the MIS transistor is a P-type MIS transistor, and

the stress-applying insulating film has a compressive stress.

10. The semiconductor device of claim 1, wherein

the first gate insulating film and the first gate electrode are formed on an active region surrounded by an isolation region of the semiconductor substrate.

11. The semiconductor device of claim 1, wherein

the first sidewall is made of silicon oxide.

12. The semiconductor device of claim 1, wherein

the first sidewall has a width of 40 nm through 60 nm at a bottom thereof.

13. The semiconductor device of claim 1, wherein

the second sidewall is made of silicon oxide.

14. The semiconductor device of claim 1, wherein

the second sidewall has a thickness of 5 nm through 10 nm.

15. The semiconductor device of claim 1, wherein

the stress-applying insulating film is made of silicon nitride.

16. The semiconductor device of claim 1, wherein

the stress-applying insulating film has a thickness of 30 nm through 50 nm.

17. The semiconductor device of claim 1, wherein

the stress-applying insulating film has a tensile stress along a gate length direction of a channel region of the semiconductor substrate located under the first gate electrode.

18. The semiconductor device of claim 1, wherein

the first gate insulating film is made of silicon oxide.

19. The semiconductor device of claim 1, wherein

the first gate electrode includes a polysilicon film.

20. The semiconductor device of claim 1, wherein

the first gate electrode contains metal.

21. The semiconductor device of claim 1, wherein

the first source/drain regions contain an N-type impurity at a concentration of 1×

10²⁰/cm³ or more.

22. The semiconductor device of claim 4, wherein

the SD extension diffusion regions contain an N-type impurity at a concentration of 1×

10¹⁹/cm³ through 1×

10²⁰/cm³.

23. The semiconductor device of claim 1 further comprising:

a first silicide layer formed on the first gate electrode; and

second silicide layers formed on the first source/drain regions,

wherein the stress-applying insulating film is formed to cover the top surface of the first silicide layer, the entire surface of the first sidewall and the top surface of the second silicide layers.

24. The semiconductor device of claim 23 further comprising:

an interlayer dielectric formed on the stress-applying insulating film; and

a contact passing through the interlayer dielectric and the stress-applying insulating film, and reaching the second silicide layers.

25. A semiconductor device having an N-type MIS transistor and a P-type MIS transistor, said N-type MIS transistor comprising:

a first gate insulating film formed on a semiconductor substrate;

a first gate electrode formed on the first gate insulating film;

a first sidewall covering the sides of the first gate electrode and the top surface of part of the semiconductor substrate and made of a first insulating film forming an L shape in cross section;

first source/drain regions formed in regions of the semiconductor substrate located outside an area covered by the first gate electrode and the first sidewall; and

a stress-applying insulating film covering the first gate electrode and the first sidewalls, and

said P-type MIS transistor comprising;

a second gate insulating film formed on the semiconductor substrate;

a second gate electrode formed on the second gate insulating film;

a second sidewall formed on the sides of the second gate electrode, forming an L shape in cross section, and made of the first insulating film;

a third sidewall formed on the second sidewall and made of a second insulating film; and

second source/drain regions formed in regions of the semiconductor substrate located outside an area covered by the second gate electrode and the second sidewall, wherein

the stress-applying insulating film has a tensile stress, and

a fourth sidewall forming a plate-like shape in cross section and made of a third insulating film is formed between the first gate electrode and the first sidewall.

26. The semiconductor device of claim 25 further comprising:

an interlayer dielectric covering the N-type MIS transistor and the P-type MIS transistor; and

a contact passing through the interlayer dielectric and reaching the second source/drain regions of the P-type MIS transistor,

wherein the contact comes into contact with the third sidewall.

27. The semiconductor device of claim 25, wherein

the N-type MIS transistor and the P-type MIS transistor form an SRAM.

28. A semiconductor device having a MIS transistor, said MIS transistor comprising:

a first gate insulating film formed on a semiconductor substrate;

a first gate electrode formed on the first gate insulating film;

a first sidewall covering the sides of the first gate electrode and the top surface of part of the semiconductor substrate and made of a first insulating film forming an L shape in cross section;

first source/drain regions formed in regions of the semiconductor substrate located outside an area covered by the first gate electrode and the first sidewall; and

a stress-applying insulating film covering the first gate electrode and the first sidewalls, wherein

a second sidewall forming a plate-like shape in cross section and made of a second insulating film is formed between the first gate electrode and the first sidewall,

the MIS transistor is an N-type MIS transistor,

the stress-applying insulating film has a tensile stress, and

a third sidewall forming an L shape in cross section and made of a third insulating film is formed between the first sidewall and the second sidewall and between the semiconductor substrate and the first sidewall.

29. The semiconductor device of claim 28, wherein

the semiconductor substrate is made of silicon, and

a gate length direction of the first gate electrode is along a <

100>

orientation of the silicon.

30. The semiconductor device of claim 28, wherein

silicide layers are formed in an upper portion of the first gate electrode and respective upper portions of the first source/drain regions.

31. The semiconductor device of claim 28, wherein

SD extension diffusion regions are formed in regions of the semiconductor substrate located under the first sidewall.

32. The semiconductor device of claim 28, wherein

the first gate insulating film and the first gate electrode are formed on an active region surrounded by an isolation region of the semiconductor substrate.

33. The semiconductor device of claim 28, wherein

the first sidewall is made of silicon oxide.

34. The semiconductor device of claim 28, wherein

the first sidewall has a width of 40 nm through 60 nm at a bottom thereof.

35. The semiconductor device of claim 28, wherein

the second sidewall is made of silicon oxide.

36. The semiconductor device of claim 28, wherein

the second sidewall has a thickness of 5 nm through 10 nm.

37. The semiconductor device of claim 28, wherein

the stress-applying insulating film is made of silicon nitride.

38. The semiconductor device of claim 28, wherein

the stress-applying insulating film has a thickness of 30 nm through 50 nm.

39. The semiconductor device of claim 28, wherein

the stress-applying insulating film has a tensile stress along a gate length direction of a channel region of the semiconductor substrate located under the first gate electrode.

40. The semiconductor device of claim 28, wherein

the first gate insulating film is made of silicon oxide.

41. The semiconductor device of claim 28, wherein

the first gate electrode includes a polysilicon film.

42. The semiconductor device of claim 28, wherein

the first gate electrode contains metal.

43. The semiconductor device of claim 28, wherein

the first source/drain regions contain an N-type impurity at a concentration of 1×

10²⁰/cm³ or more.

44. The semiconductor device of claim 31, wherein

the SD extension diffusion regions contain an N-type impurity at a concentration of 1×

10¹⁹/cm³ through 1×

10²⁰/cm³.

45. The semiconductor device of claim 28 further comprising:

a first silicide layer formed on the first gate electrode; and

second silicide layers formed on the first source/drain regions,

wherein the stress-applying insulating film is formed to cover the top surface of the first silicide layer, the entire surface of the first sidewall and the top surface of the second silicide layers.

46. The semiconductor device of claim 45 further comprising:

an interlayer dielectric formed on the stress-applying insulating film; and

a contact passing through the interlayer dielectric and the stress-applying insulating film, and reaching the second silicide layers.

47. A semiconductor device having a MIS transistor, said MIS transistor comprising:

a first gate insulating film formed on a semiconductor substrate;

a first gate electrode formed on the first gate insulating film;

a first sidewall covering the sides of the first gate electrode and the top surface of part of the semiconductor substrate and made of a first insulating film forming an L shape in cross section;

first source/drain regions formed in regions of the semiconductor substrate located outside an area covered by the first gate electrode and the first sidewall; and

a stress-applying insulating film covering the first gate electrode and the first sidewalls, wherein

a second sidewall forming a plate-like shape in cross section and made of a second insulating film is formed between the first gate electrode and the first sidewall,

the MIS transistor is a P-type MIS transistor,

the stress-applying insulating film has a compressive stress, and

a third sidewall forming an L shape in cross section and made of a third insulating film is formed between the first sidewall and the second sidewall and between the semiconductor substrate and the first sidewall.