Chip assembly including package element and integrated circuit chip

• US 7,737,513 B2
• Filed: 05/30/2007
• Issued: 06/15/2010
• Est. Priority Date: 05/30/2007
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: White, Charles, Haba, Belgacem, Nystrom, Michael J.
• Primary Examiner(s): Williams; Alexander O
• Application Number:
  US11/809,213
• Publication Number:
  US 20080296709A1
• Time in Patent Office: 1,112 Days
• Field of Search: 257/416, 257/E29.324, 257/E21.505, 257/737, 257/738, 257/698, 257/734, 257/772, 257/782
• US Class Current: 257/416
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/166 : Material
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

The present invention provides an integrated circuit chip assembly and a method of manufacturing the same. The assembly includes a package element having a top surface and an integrated circuit chip having a top surface, a bottom surface, edge surface between the top and bottom surfaces, and contacts exposed at the top surface. The package element is disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip. At least one spacer element resides between the top surface of the package element and the bottom surface of the chip. According to one embodiment, the at least one spacer element may form a substantially closed cavity between the package element and the integrated circuit chip. According to another embodiment, first conductive features may extend from the contacts of the chip along the top surface, and at least some of said first conductive features extend along at least one of the edge surfaces of the chip.

Claims

1. An assembly, comprising:

a package element having a top surface;

an integrated circuit chip having a top surface, a bottom surface, and contacts exposed at the top surface, the package element being disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip;

at least one spacer element residing between the top surface of the package element and the bottom surface of the chip, the at least one spacer element forming a substantially closed cavity between the package element and the chip; and

first conductive features extending from the contacts of the chip along the top surface, extending along at least one edge surface of the chip and extending from the at least one edge surface of the chip to the top surface of the package element.

2. The assembly of claim 1, further comprising a bonding material residing on at least some of the first conductive features.

3. The assembly of claim 1, further comprising second conductive features extending along the package element.

4. The assembly of claim 3, wherein the first and second conductive features are electrically connected.

5. The assembly of claim 3, further comprising an antenna disposed within the cavity, the antenna being electrically connected to the second conductive features.

6. The assembly of claim 3, further comprising elements operable to collectively function as a microelectromechanical system disposed within the cavity, at least one of the elements being electrically connected to the second conductive features.

7. The assembly of claim 3, further comprising elements operable to collectively function as a surface acoustic wave device disposed within the cavity, at least one of the elements being electrically connected to the second conductive features.

8. The assembly of claim 1, wherein the package element includes silicon.

9. The assembly of claim 1, wherein the package element includes glass.

10. An assembly, comprising:

a package element having a top surface;

an integrated circuit chip having a top surface, a bottom surface, edge surfaces extending between the top and bottom surfaces and contacts exposed at the top surface, the package element being disposed below the chip with the top surface of the package element facing toward the bottom surface of the chip;

at least one spacer element residing between the top surface of the package element and the bottom surface of the chip, the at least one spacer element forming a cavity between the package element and the integrated circuit chip; and

first conductive features extending from the contacts of the chip along the top surface, at least some of said first conductive features extending along at least one of the edge surfaces of the chip and at least some of the first conductive features extending from the at least one of the edge surfaces of the chip to the top surface of the package element.

11. The assembly of claim 10, wherein the cavity is substantially closed.

12. The assembly of claim 10, further comprising second conductive features extending between the package element and integrated circuit chip into the cavity.

13. The assembly of claim 10, further comprising a bonding material residing on at least some of the first conductive features.

14. The assembly of claim 12, wherein the first conductive features and the second conductive features are connected.

15. The assembly of claim 10, further comprising an antenna disposed within the cavity, the antenna being electrically connected to the second conductive features.

16. The assembly of claim 10, further comprising elements operable to collectively function as a microelectromechanical system disposed within the cavity, at least one of the elements being electrically connected to the second conductive features.

17. The assembly of claim 10, further comprising elements operable to collectively function as a surface acoustic wave device disposed within the cavity, at least one of the elements being electrically connected to the second conductive features.

18. The assembly of claim 10, wherein the package element includes silicon.

19. The assembly of claim 10, wherein the package element includes glass.