Dual damascene integration of ultra low dielectric constant porous materials

• US 7,737,561 B2
• Filed: 01/03/2008
• Issued: 06/15/2010
• Est. Priority Date: 08/21/2003
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tyberg, Christy S, Kumar, Kaushik A, Malone, Kelly
• Primary Examiner(s): Weiss; Howard
• Application Number:
  US11/968,929
• Publication Number:
  US 20080099923A1
• Time in Patent Office: 894 Days
• Field of Search: 257/774, 257/759, 257/E21.579, 257/E23.167
• US Class Current: 257/774
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: G03F 7/0002 Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous line level low-k dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous line level low-k dielectric; a second thin non-porous via level low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

Claims

1. A microprocessor comprising:

electrical interconnections having an RC delay comprising ultra low dielectric constant materials providing a circuit speed, said electrical interconnections comprise;

a dual damascene interconnect structure, comprising;

a patterned multilayer of dielectrics on a substrate, comprising;

a cap layer;

a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls;

an etch stop layer;

a first porous line level low-k dielectric layer having thereon metal line conductors with a bottom portion and sidewalls;

a polish stop layer over said first porous low-k dielectric;

a second thin non-porous via level low-k dielectric layer for coating and planarizing the line and via sidewalls; and

a liner material between said metal via and line conductors and said first non-porous via level low-k dielectric layer, said first porous line level low-k dielectric layer, and said second thin non-porous via level low-k dielectric layer,

wherein said second thin non-porous via level low-k dielectric layer has a composition that is covalently bonded with said first non-porous via level low-k dielectric layer, said first porous line level low-k dielectric layer, and said etch stop layer.

2. The microprocessor of claim 1, wherein said first porous line level low-k dielectric layer and said first non-porous via level low-k dielectric layers form covalent bonds with said etch stop layer.

3. The microprocessor of claim 1, wherein said first non-porous via level low-k dielectric layer has a material that is covalently bound to said etch stop layer.

4. The microprocessor of claim 3, wherein said covalently bound material is selected from the group consisting of non-porous low k dielectric materials, organic material and any combinations thereof.

5. The microprocessor of claim 1, wherein said first porous line level low-k dielectric layer has a material that is covalently bound to said etch stop layer.

6. The microprocessor of claim 1, wherein said first porous line level low-k dielectric layer has a material that is a porous organic material.

7. The microprocessor of claim 1, wherein said first porous line level low-k dielectric material has pores with a pore size greater than 2 nm.

8. The microprocessor of claim 1, wherein said first non-porous via level low-k dielectric and said first porous line level low-k dielectric layers have identical chemical compositions.

9. The microprocessor of claim 1, wherein said first non-porous via level low-k dielectric layer, said first porous line level low-k dielectric and said second thin non-porous via level low-k dielectric layers are organic.

10. The microprocessor of claim 1, wherein said etch stop layer and said second thin non-porous via level low-k dielectric layers contain silicon.

11. The microprocessor of claim 1, wherein said etch stop layer contains silicon.

12. The microprocessor of claim 1, wherein said second thin non-porous via level low-k dielectric layer and said first non-porous via level low-k dielectric layer have identical compositions.

13. The microprocessor of claim 1, wherein said second thin non-porous via level low-k dielectric layer has the same chemical composition as said etch stop layer.

14. The microprocessor of claim 1, wherein said second thin non-porous via level low-k dielectric layer has a thickness of about 20 Å

to about 100 Å

.

15. The microprocessor of claim 1, wherein said second thin non-porous low-k dielectric layer is selected from the group consisting of organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, silicon carbides, silicon oxides, and any combinations thereof.

16. The microprocessor of claim 1, wherein said second thin non-porous via level low-k dielectric layer conformally coats the line and via sidewalls.

17. The microprocessor of claim 1, wherein said first porous line level low-k dielectric layer has a thickness of about 600 Å

to about 5000 Å

.

18. The microprocessor of claim 1, wherein said etch stop layer has a chemical composition comprising silicon, carbon, oxygen and hydrogen.

19. The microprocessor of claim 1, wherein said etch stop layer is comprised of a spin-on material with etch selectivity to said first porous line level low-k dielectric.

20. The microprocessor of claim 1, wherein said etch stop layer is selected from the group consisting of organo silsesquioxanes, hydrido silsesquioxanes, hydridoorgano silsesquioxanes, siloxanes, silicon carbides, silicon oxides and any combinations thereof.

21. The microprocessor of claim 1, wherein said etch stop layer has a thickness of about 50 Å

to about 600 Å

.

22. The microprocessor of claim 1, wherein said liner material comprises one or more metals selected from the group consisting of:

Ti, TiN, Ta, TaN, W, TiW, TaSiN, WN, nitrides thereof and any combinations thereof.

23. The microprocessor of claim 1, wherein said liner material is a material deposited by sputter deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), ionized physical vapor deposition (Ionized PVD), atomic layer deposition (ALD) and any combinations thereof.

24. The microprocessor of claim 1, wherein said liner material is continuous and does not penetrate into said first porous line level low-k dielectric layer.

25. The microprocessor of claim 1, wherein said second thin non-porous via level low-k dielectric layer is arranged substantially perpendicular to said first non-porous via level low-k dielectric layer, said first porous line level low-k dielectric layer, and said etch stop layer.