Universal digital block interconnection and channel routing

• US 7,737,724 B2
• Filed: 12/27/2007
• Issued: 06/15/2010
• Est. Priority Date: 04/17/2007
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren, Mohammed, Haneef, Sullam, Bert
• Primary Examiner(s): Tran, Anh Q
• Application Number:
  US11/965,291
• Publication Number:
  US 20080258759A1
• Time in Patent Office: 901 Days
• Field of Search: 326 38- 41, 326/47
• US Class Current: 326/41
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4009 with data restructuring
• CPC Class Codes: H03K 19/177 arranged in matrix form

Abstract

A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O.

Claims

1. An apparatus, comprising:

an array of digital blocks; and

a programmable interconnect matrix including horizontal channels that programmably couple different groups of one or more digital blocks together and segmentation elements that programmably interconnect different horizontal channels together, wherein the digital blocks each comprise a first group of uncommitted logic elements that are programmable into different logic functions and a second group of dedicated logic elements that together form a programmable arithmetic sequencer.

2. The apparatus according to claim 1 wherein the segmentation elements include:

horizontal segmentation switches that programmably couple together the horizontal channels in a same row; and

vertical segmentation switches that programmably couple together the horizontal channels in different rows.

5. The apparatus according to claim 1 further comprising:

programmably selectable channel switches configured to connect different selectable signals from the digital bocks to associated horizontal channels; and

programmable tri-state buffers in the segmentation elements configured to selectively couple together and drive signals between the different horizontal channels.

6. The apparatus according to claim 1 further comprising a Random Access Memory (RAM) configured to programmably control how the different digital blocks are coupled together through the interconnection matrix.

7. The apparatus according to claim 1 including Inputs and Outputs (I/Os) that are initially not dedicated to any particular digital blocks and that are programmably coupled to different selectable digital blocks through different selectable routes in the interconnect matrix.

3. An apparatus, comprising:

an array of digital blocks;

a programmable interconnect matrix including horizontal channels that programmably couple different groups of one or more digital blocks together and segmentation elements that programmably interconnect different horizontal channels together; and

vertical channels that programmably interconnect the horizontal channels in different rows, wherein the horizontal channels provide more connectivity between the digital blocks located in the same rows than connectivity provided by the vertical channels between the digital blocks located in different rows.

4. An apparatus, comprising:

an array of digital blocks; and

a programmable interconnect matrix including horizontal channels that programmably couple different groups of one or more digital blocks together and segmentation elements that programmably interconnect different horizontal channels together,

wherein two digital blocks in a same digital block pair are tightly coupled together to common routes in a same associated horizontal channel and different digital block pairs are less tightly coupled together through the segmentation elements.

8. An apparatus, comprising:

an array of digital blocks; and

a programmable interconnect matrix including horizontal channels that programmably couple different groups of one or more digital blocks together and segmentation elements that programmably interconnect different horizontal channels together; and

a micro-controller system programmably coupled to the different digital blocks and to different selectable Inputs/Outputs (I/Os) through the interconnect matrix.

9. The apparatus according to claim 8 wherein:

the micro-controller system includes a micro-controller, an interrupt controller, and Direct Memory Access (DMA) controller;

interrupt requests are programmably coupled between the interrupt controller and different selectable digital blocks or different selectable I/Os through the interconnect matrix; and

DMA requests are programmably coupled between the DMA controller and different selectable digital blocks or different selectable I/Os through the interconnect matrix.

10. The apparatus according to claim 9 wherein the micro-controller system, digital blocks, I/Os, and interconnect matrix are all located in a same integrated circuit.

11. An integrated circuit, comprising:

a micro-controller system;

a programmable interconnect including horizontal channels and vertical channels;

a memory device accessible by the micro-controller to control how functional elements in the integrated circuit connect to the horizontal channels and control how the horizontal channels and vertical channels connect to each other;

programmably configurable digital blocks that are selectively coupled to the horizontal channels according to bits loaded into the memory device; and

undedicated external input and output pins that are programmably coupled to different inputs and outputs in the micro-controller system through the programmable interconnect and also programmably coupled to different selectable functional elements in the different digital blocks through the programmable interconnect.

12. The integrated circuit according to claim 11 further comprising segmentation elements having:

horizontal segmentation switches that programmably couple together the horizontal channels in a same row; and

vertical segmentation switches that programmably couple together the horizontal channels in different rows.

13. The integrated circuit according to claim 11 further comprising:

channel switching elements that are programmably activated by a first set of memory cells in the memory device for connecting the horizontal channels to the digital blocks; and

programmable tri-state buffers that are programmably activated by a second set of memory cells in the memory device for connecting together the horizontal channels.

14. An integrated circuit, comprising:

a micro-controller system;

a programmable interconnect including horizontal channels and vertical channels; and

a memory device accessible by the micro-controller to control how functional elements in the integrated circuit connect to the horizontal channels and control how the horizontal channels and vertical channels connect to each other;

an interrupt controller that receives interrupt requests through the programmable interconnect from different selectable digital blocks or different selectable I/Os; and

a Direct Memory Access (DMA) controller that receives DMA requests through the programmable interconnect from different selectable digital blocks or different selectable I/Os.

15. A method, comprising:

providing an interconnect matrix;

programming the interconnect matrix to connect different functional elements to associated local routing channels;

programming the interconnect matrix to interconnect different local routing channels together;

programming the interconnect matrix to further connect different local routing channels to each other through general routing channels;

writing a first set of values into a configuration memory that control connections between the functional elements and the associated local routing channels;

writing a second set of values into the configuration memory that control the interconnections between different local routing channels; and

writing a third set of values into the configuration memory that control the interconnections between the local routing channels and the general routing channels.

16. A method, comprising:

providing an interconnect matrix;

programming the interconnect matrix to connect different functional elements to associated local routing channels;

programming the interconnect matrix to interconnect different local routing channels together;

programming the interconnect matrix to further connect different local routing channels to each other through general routing channels; and

programming different paths through the interconnect matrix that connect different external pins or different internal functional elements to a same interrupt line on an internal interrupt controller;

or

programming different paths through the interconnect matrix that connect different external pins or different internal functional elements to a same Direct Memory Access (DMA) line on an internal DMA controller.