Cascode amplifier and method for controlling current of cascode amplifier

• US 7,737,790 B1
• Filed: 04/09/2009
• Issued: 06/15/2010
• Est. Priority Date: 04/09/2009
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Lin, Yu-Hsin, Chen, Yen-Horng
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US12/421,615
• Time in Patent Office: 432 Days
• Field of Search: 330/311, 330/296, 330/253
• US Class Current: 330/311
• CPC Class Codes: H03F 1/223 with MOSFET's

Abstract

A cascode amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor and a bias circuit. Each of the transistors has a gate electrode, a first electrode and a second electrode, a first electrode of the first transistor is coupled to a second electrode of the second transistor, a first electrode of the third transistor is coupled to a second electrode of the fourth transistor, and gate electrodes of the third and the fourth transistors are coupled to gate electrodes of the first and the second transistors, respectively. The bias circuit is coupled to the first electrode of the fourth transistor, and is used for biasing a voltage level at the first electrode of the fourth transistor to make the second and the fourth transistors operate in a same region.

Claims

1. A cascode amplifier, comprising:

an input signal terminal;

an output signal terminal;

a first transistor and a second transistor, wherein each of the first and the second transistors has a gate electrode, a first electrode and a second electrode, the first electrode of the first transistor is coupled to the second electrode of the second transistor, the gate electrode of the first transistor is coupled to the input signal terminal, and the first electrode of the second transistor is coupled to the output signal terminal;

a third transistor and a fourth transistor, wherein each of the third and the fourth transistors has a gate electrode, a first electrode and a second electrode, the first electrode of the third transistor is coupled to the second electrode of the fourth transistor, and the gate electrodes of the third and the fourth transistors are coupled to the gate electrodes of the first and the second transistors, respectively; and

a bias circuit, coupled to the first electrode of the fourth transistor, for biasing a voltage level at the first electrode of the fourth transistor to make the second and the fourth transistors operate in a same region.

2. The cascode amplifier of claim 1, wherein the bias circuit is arranged to make the voltage level at the first electrode of the fourth transistor substantially equal a voltage level at the first electrode of the second transistor.

3. The cascode amplifier of claim 1, wherein the first, second, third and fourth transistors are metal-oxide semiconductor (MOS) transistors, and the bias circuit is arranged to make the second and the fourth transistors operate in a saturation region.

4. The cascode amplifier of claim 3, wherein the bias circuit is arranged to make the voltage level at the first electrode of the fourth transistor substantially equal a voltage level at the first electrode of the second transistor.

5. The cascode amplifier of claim 1, wherein the bias circuit comprises:

a fifth transistor, wherein a gate electrode of the fifth transistor is coupled to the first electrode of the fourth transistor; and

a current source, coupled to the fifth transistor, for providing a predetermined current to the fifth transistor.

6. The cascode amplifier of claim 5, wherein the gate electrode of the third transistor is coupled between the fifth transistor and the current source;

and

the gate electrodes of the first and third transistors are coupled to each other through a resistor coupled.

7. A method for controlling a current of a cascode amplifier, comprising:

providing a first transistor and a second transistor, wherein each of the first and the second transistors has a gate electrode, a first electrode and a second electrode, the first electrode of the first transistor is coupled to the second electrode of the second transistor, the gate electrode of the first transistor is coupled to an input signal terminal, and the first electrode of the second transistor is coupled to an output signal terminal;

providing a third transistor and a fourth transistor, wherein each of the third and the fourth transistors has a gate electrode, a first electrode and a second electrode, the first electrode of the third transistor is coupled to the second electrode of the fourth transistor, and the gate electrodes of the third and the fourth transistors are coupled to the gate electrodes of the first and the second transistors, respectively; and

biasing a voltage level at the first electrode of the fourth transistor to make the second and the fourth transistors operate in a same region.

8. The method of claim 7, wherein the step of biasing the voltage level at the first electrode of the fourth transistor to make the second and the fourth transistors operate in the same region comprises:

biasing the voltage level at the first electrode of the fourth transistor to make the voltage level at the first electrode of the fourth transistor substantially equal a voltage level at the first electrode of the second transistor.

9. The method of claim 7, wherein the first, second, third and fourth transistors are metal-oxide semiconductor (MOS) transistors, and the step of biasing the voltage level at the first electrode of the fourth transistor to make the second and the fourth transistors operate in the same region comprises:

biasing the voltage level at the first electrode of the fourth transistor to make the second and the fourth transistors operate in a saturation region.

10. The method of claim 9, wherein the step of biasing the voltage level at the first electrode of the fourth transistor to make the second and the fourth transistors operate in the same region comprises:

biasing the voltage level at the first electrode of the fourth transistor to make the voltage level at the first electrode of the fourth transistor substantially equal a voltage level at the first electrode of the second transistor.

11. The method of claim 7, wherein the step of biasing the voltage level at the first electrode of the fourth transistor to make the second and the fourth transistors operate in the same region comprises:

providing a fifth transistor, wherein a gate electrode of the fifth transistor is coupled to the first electrode of the fourth transistor; and

providing a current source, wherein the current source provides a predetermined current to the fifth transistor.

12. The method of claim 11, wherein the gate electrode of the third transistor is coupled between the fifth transistor and the current source;

and the gate electrodes of the first and third transistors are coupled to each other through a resistor coupled.