Multiple use memory chip

• US 7,738,304 B2
• Filed: 10/11/2005
• Issued: 06/15/2010
• Est. Priority Date: 07/10/2002
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Maayan, Eduardo
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US11/246,193
• Publication Number:
  US 20060152975A1
• Time in Patent Office: 1,708 Days
• Field of Search: 365/185.33, 365/63, 365/185.17, 365/185.03
• US Class Current: 365/185.33
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data

Abstract

A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array. Each array may store Flash, EEPROM or both types of bits.

Claims

1. A non-volatile memory (“

NVM”

) die comprising;

a first set of charge trapping type NVM cells adapted to be operated as a first type of flash memory;

a second set of NVM cells adapted to be operated as a second type of flash memory; and

a controller adapted to operate said first set as a first type of flash memory and to operate said second set of cells as a second type of flash memory.

2. The die according to claim 1, wherein at least one of said sets is adapted to be operated as NAND type Flash memory.

3. The die according to claim 1, wherein at least one of said sets is adapted to be operated as NOR type Flash memory.

4. The die according to claim 1, wherein at least one set of cells comprises at least one multi-bit-per-cell cell.

5. The die according to claim 4, wherein at least one set of cells comprises both single-bit-per-cell and multi-bit-per-cell cells.

6. The die according to claim 1, wherein at least one set of cells is adapted to be operated as multi-bit-per-cell cells.

7. The die according to claim 1, wherein at least one set of cells is adapted to be operated as single-bit-per-cell cells.

8. The die according to claim 1, wherein at least one set of cells is adapted to be operated as multi-bit-per-cell cells, and wherein at least one cells from the at least one set of cells stores one of its bits in multi level made.

9. The die according to claim 1, wherein at least one set of cells is adapted to be operated as multi-bit-per-cell cells, and wherein at least one cell of the at least one set of cells stores one of its bits in single level mode.

10. A method of operating a non-volatile memory (“

NVM”

) device comprising;

operating a first set of charge rapping type NVM cells as a first type of flash memory and operating a said second set of charge trapping type NVM cells as a second type of flash memory.

11. The method according to claim 10, wherein at least one of said sets is operated as NAND type memory.

12. The method according to claim 10, wherein at least one of said sets is operated as NOR type memory.

13. The method according to claim 10, wherein at least one set of cells is operated as code flash.

14. The method according to claim 10, wherein at least one set of cells is operated as data flash.

15. The method according to claim 10, wherein at least one set of cells is operated as multi-bit-per-cell cells.

16. The method according to claim 10, wherein at least one set of cells is operated as single-bit-per-cell cells.

17. A non-volatile memory (“

NVM”

) die comprising;

a first set of charge trapping type NVM cells adapted to be operated as NOR type memory; and

a second set of charge trapping type NVM cells adapted to be operated as NAND type memory.

18. The die according to claim 17, wherein said charge trapping region is comprised of a dielectric.

19. The die according to claim 18, wherein said dielectric is comprised of a nitride material.

20. The die according to claim 19, wherein said dielectric is silicon nitride.