Semiconductor memory devices having optimized memory block organization and data line routing for reducing chip size and increasing speed
First Claim
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1. A semiconductor memory device, comprising:
- a memory array comprising a plurality of memory banks, wherein each bank is divided into a plurality of sub-banks;
a first set of data I/O lines extending in a first direction between sub-banks, wherein the first set of data I/O lines are formed in a first metallization level;
a second set of data I/O lines extending in a second direction, perpendicular to the first direction, across one sub-bank, wherein the second set of data I/O lines are formed in a second metallization level and connected to the first set of data I/O lines; and
a third set of data I/O lines extending in the first direction across the one sub-bank, wherein the third set of data I/O lines are formed in a third metallization level and connected to the second set of data I/O lines.
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Abstract
Multi-bank semiconductor memory devices are provided having optimized memory block layouts and data line routing to enable chip size reduction and increase operating memory access speed.
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Citations
17 Claims
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1. A semiconductor memory device, comprising:
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a memory array comprising a plurality of memory banks, wherein each bank is divided into a plurality of sub-banks; a first set of data I/O lines extending in a first direction between sub-banks, wherein the first set of data I/O lines are formed in a first metallization level; a second set of data I/O lines extending in a second direction, perpendicular to the first direction, across one sub-bank, wherein the second set of data I/O lines are formed in a second metallization level and connected to the first set of data I/O lines; and a third set of data I/O lines extending in the first direction across the one sub-bank, wherein the third set of data I/O lines are formed in a third metallization level and connected to the second set of data I/O lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A multi-bank integrated circuit memory device comprising a plurality of independently controlled memory banks, wherein each memory bank is divided into a plurality of sub-banks arranged in a plurality of rows and columns of sub-banks of memory cells, wherein the sub-banks of each bank being located along the same row of sub-banks of memory cells;
wherein at least two banks have rows of subbanks that are adjacent to each other with word line decode circuitry interposed there between. - View Dependent Claims (11, 12, 13)
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14. A multi-bank integrated circuit memory device comprising a plurality of independently controlled memory banks, wherein each memory bank is divided into a plurality of sub-banks arranged in a plurality of rows and columns of sub-banks of memory cells, wherein the sub-banks of each bank being located along the same row of sub-banks of memory cells,
wherein the multi-bank integrated circuit memory device further comprising: -
a first set of data I/O lines extending in a first direction between sub-banks, wherein the first set of data I/O lines are formed in a first metallization level; a second set of data I/O lines extending in a second direction, perpendicular to the first direction, across one sub-bank, wherein the second set of data I/O lines are formed in a second metallization level and connected to the first set of data I/O lines; and a third set of data I/O lines extending in the first direction across the one sub-bank, wherein the third set of data I/O lines are formed in a third metallization level and connected to the second set of data I/O lines. - View Dependent Claims (15, 16, 17)
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Specification