Multiplexed RF isolator

• US 7,738,568 B2
• Filed: 06/30/2007
• Issued: 06/15/2010
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Alfano, Donald E., Dupuis, Timothy, Etter, Brett
• Primary Examiner(s): Ahn; Sam K
• Application Number:
  US11/772,162
• Publication Number:
  US 20080031286A1
• Time in Patent Office: 1,081 Days
• Field of Search: 375/257, 375/258, 375/259, 375/260, 375/295, 375/316, 375/354, 375/355, 375/356, 375/282, 375/357, 375/361, 375/369, 375/372, 375/373, 375/374, 370/395.62, 370/498, 370/503, 370/507, 370/535, 370/537, 370/542, 455/265, 702/89, 713/375, 713/400
• US Class Current: 375/258
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/1204 : Optical Diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/33523 : with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: H04B 2203/542 : using zero crossing information
• CPC Class Codes: H04B 3/542 : the information being in digital form
• CPC Class Codes: H04B 3/548 : the power on the line being DC arrangements for feeding power H04L12/10; extracting feeding power from signals H04L25/02
• CPC Class Codes: H04B 3/56 : Circuits for coupling, blocking, or by-passing of signals
• CPC Class Codes: H04L 25/0266 : Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling

Abstract

A system for providing multiple communication channels over a single voltage isolation link includes first circuitry for multiplexing a plurality of digital data inputs from a plurality of communication channels onto the single voltage isolation link. Second circuitry de-multiplexes the plurality of digital data inputs from the single voltage isolation link to the plurality of communication channels. An RF isolator is used for providing the single voltage isolation link.

Claims

1. An integrated circuit isolator providing for communications of multiple digital data signals over a common communications channel across a voltage isolation barrier, comprising:

an integrated circuit package having a plurality of input pins for receiving respective ones of a plurality of input digital data signals and a plurality of output pins for outputting a plurality of respective output digital data signals;

a transformer disposed between the input and output pins to provide the voltage isolation barrier within the package between the plurality of input pins and the plurality of output pins and for passing the input digital signals between the plurality of input pins and the plurality of output pins over the common communications channel, wherein the voltage isolation barrier provides voltage isolation of up to 5000 volts;

a time multiplexer to time multiplex the input digital data signals and transmit the time multiplexed input digital data signals across the transformer from one side thereof; and

a time demultiplexer for receiving from the transformer on an other side thereof, and voltage isolated from the one side thereof, the multiplexed input digital data signals and demultiplexing the received multiplexed input digital data signals as a reconstructed sample of the respective output digital data signals and a latch for latching the reconstructed sample onto the respective one of the plurality of output pins.

2. The isolator of claim 1, wherein the time multiplexer comprises first circuitry disposed within the package and on the one side of the transformer and including:

a sampling circuit for sequentially sampling each of the plurality of input digital data signals received on the plurality of input pins in defined time slots during a sampling frame; and

a transmitter for transmitting in a serial format the sampled input digital data signals to the common communications channel across the transformer.

3. The isolator of claim 2, wherein the time demultiplexer comprises second circuitry disposed within the package and on the other side of the transformer and including:

a receiver for receiving from the common communications channel on the other side of the transformer input the serially transmitted sampled input digital data signals, and

a demultiplexer for demultiplexing the received sampled input digital data signals to provide the plurality of output digital data signals for interface to the plurality of output pins, and

a communications interface for connecting the common communications channel transmit output to the common communications receive input across the isolation barrier to form the common communications channel, such that voltage isolation is maintained between the first and second circuitry within the package.

4. The isolator of claim 1, wherein said integrated circuit package includes a first integrated circuit for containing the time multiplexer and a second integrated circuit for containing the time demultiplexer, the first and second integrated circuits voltage isolated from each other within said package.

5. The isolator of claim 4, wherein said transformer includes a first coil as a primary winding and a second coil as a secondary winding, the first and second coils separated by a dielectric boundary, and wherein at least said first coil is formed on one of the first and second circuits.

6. The isolator of claim 5, wherein the first coil is formed on the first integrated circuit and the second coil is formed on the second integrated circuit.

7. The isolator of claim 6, and further including an intermediary winding for coupling the first coil to the second coil and separated form both the first and second coils by the dielectric boundary.

8. The isolator of claim 4, wherein the time multiplexer includes an RF transmitter for driving the transformer on the one side thereof with an RF signal encoded with the time multiplexed input digital data signals in accordance with a serial digital data protocol, and the time demultiplexer including an RF receiver for receiving the RF signal from the other side of the transformer.

9. An integrated circuit isolator providing for communications of multiple digital data signals over a common communications channel across a voltage isolation barrier, comprising:

an integrated circuit package having a plurality of input pins for receiving respective ones of a plurality of input digital data signals on one side of the isolation barrier and a plurality of output pins for outputting a plurality of respective output digital data signals on the other side of the isolation barrier;

first circuitry disposed within the package and on the one side of the isolation barrier and including;

a sampling circuit for sampling select ones of the input digital data signals during a given time slot at a sampling rate defined by a sample clock;

a framer circuit for encoding the sampled data for serial transmission on the common communications channel;

the sampling circuit including a latching shift register for receiving each of the plurality of digital data input signals in parallel, the latching shift register latching a value on each of the plurality of input digital data signals to a present data value responsive to a first control input, the latching shift register further serially shifting the latched present data value of each of the plurality of input digital data signals from the latching shift register to the framer circuit responsive to the sampling clock on a clock signal input;

a multiplexer for multiplexing each of the plurality of input digital data signals received on the plurality of input pins, and

a transmitter for transmitting to a common communications channel transmit output on the one side of the isolation barrier the multiplexed input digital data signals;

second circuitry disposed within the package and on the other side of the isolation barrier and including;

a receiver for receiving from a common communications channel receive input on the other side of the isolation barrier the multiplexed input digital data signals, and

a demultiplexer for demultiplexing the received multiplexed input digital data signals to provide the plurality of output digital data signals for interface to the plurality of output pins; and

a communications interface for connecting the common communications channel transmit output to the common communications receive input across the isolation barrier to form the common communications channel, such that voltage isolation is maintained between the first and second circuitry within the package.

10. The isolator of claim 9, wherein the framer circuit Manchester encodes the data for serial transmission.

11. The isolator of claim 9, wherein the framer circuit further generates a start bit to indicate a beginning of a frame responsive to a second control signal and a stop bit indicating an end of frame responsive to a third control signal, such that the frame represents the given time slot.

12. The isolator of claim 11 further including a state machine for generating the second control signal, the third control signal and the clock signal input.

13. The isolator of claim 12, wherein the state machine generates the second control signal responsive to the first control signal latching the present data values of the plurality of input digital data signals into the latching shift register.

14. The isolator of claim 12, wherein the state machine generates the third control signal responsive a determination that all of the present data values of the plurality of input digital data signals have all been shifted to the framer circuit.

15. The isolator of claim 12 further including a clock circuit, wherein the clock signal input is generated by the state machine responsive to an output of the clock circuit.

16. The isolator of claim 9, wherein the sampled data is encoded with timing information embedded therein representing the sampling clock and the second circuitry further comprises:

a synchronizer circuit for decoding data serially received from the single voltage isolation link into clock data and present data values and for generating a Write Enable signal once an entire frame of data has been received;

a shift register for serially receiving the clock data and the present data values and for outputting the received present data values in parallel; and

an output register for storing the present data values received in parallel from the shift register responsive to the Write Enable control signal for interface to respective ones of the output pins.

17. The isolator of claim 16, wherein the synchronizer further generates a signal indicating outputs of the output register have stabilized.

18. The isolator of claim 16, wherein the sampled data is Manchester encoded and the synchronizer Manchester decodes the decoded data.

19. A system for providing multiple communications channels over a single voltage isolation link, comprising:

a framer circuit for Manchester encoding data for serial transmission on the single voltage isolation link, wherein the framer circuit further generates a start bit to indicate a beginning of a frame responsive to a second control signal and a stop bit indicating an end of frame responsive to a third control signal;

a latching shift register for receiving each of a plurality of digital data inputs from a plurality of communications channels in parallel, the latching shift register latching a value on each of the plurality of digital data inputs to a present data value responsive to a first control input, the latching shift register further serially shifting the latched present data value of each of the plurality of digital data inputs from the latching shift register to the framer circuit responsive to a clock signal input;

a synchronizer circuit for Manchester decoding data serially received from the single voltage isolation link into clock data and the present data values responsive to detection of the start bit and for generating a write enable signal responsive to detection of the stop bit;

a shift register for serially receiving the clock data and the present data values and for outputting the received present data values in parallel;

an output register for storing the present data values received in parallel from the shift register responsive to the write enable control signal; and

an RF isolator for providing the single voltage isolation link.

20. The system of claim 19 further including a state machine for generating the second control signal responsive to the first control signal latching the present values of the plurality of data inputs into the latching shift register, and for generating the third control signal responsive to a determination that all of the present values of the plurality of data inputs have been shifted to the framer circuit and the clock signal input.

21. The system of claim 20 further including a clock circuit, wherein the clock signal input is generated by the state machine responsive to an output of the clock circuit.

22. The system of claim 19, wherein the synchronizer further generates a signal indicating outputs of the output register have stabilized.