Descriptor transfer logic

• US 7,739,426 B1
• Filed: 10/31/2006
• Issued: 06/15/2010
• Est. Priority Date: 10/31/2005
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Rosen, Jonathan, Steiss, Donald E., Fingerhut, John A., Burns, Barry S., White, Christopher E.
• Primary Examiner(s): Park; Ilwoo
• Assistant Examiner(s): Hassan; Aurangzeb
• Application Number:
  US11/555,066
• Time in Patent Office: 1,323 Days
• Field of Search: None
• US Class Current: 710/52
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways

Abstract

A processing engine includes descriptor transfer logic that receives descriptors generated by a software controlled general purpose processing element. The descriptor transfer logic manages transactions that send the descriptors to resources for execution and receive responses back from the resources in response to the sent descriptors. The descriptor transfer logic can manage the allocation and operation of buffers and registers that initiate the transaction, track the status of the transaction, and receive the responses back from the resources all on behalf of the general purpose processing element.

Claims

1. An apparatus, comprising:

descriptor transfer logic coupled between a programmable general purpose processing element and resources and configured to receive descriptors generated by the processing element and manage transactions that sends the descriptors to the resources for execution and receives responses back from the resources in response to the sent descriptors,

the descriptor transfer logic further configured to manage the allocation and operation of buffers and registers that initiate the transaction, track the status of the transaction, and receive the responses back from the resources independently from the processing element, the descriptor transfer logic including a Command First-In First-Out buffer (CFIFO) configured to buffer multiple different batched resource instructions contained in the same or multiple different descriptors received from the processing element, and the descriptor transfer logic further configured to manage the transfer of the resource instructions from the CFIFO to the resources.

2. The apparatus according to claim 1 wherein:

the processing element comprises a Central Processing Unit (CPU) configured to generate the descriptors independently of the descriptor transfer logic;

the resources comprise multiple different computer or co-processing elements that process the resource instructions in the descriptors independently of the CPU;

the descriptor transfer logic is coupled between the CPU and through an interconnect to the multiple different computer or co-processing elements;

the CFIFO includes an input coupled to the CPU and an output coupled through the interconnect to the multiple different computer or co-processing elements; and

the descriptor transfer logic manages for the CPU monitoring the status of the resource instructions sent from the CFIFO to the resources.

3. The apparatus according to claim 2 wherein the descriptor transfer logic includes a send register that when written to by the CPU indicates to the descriptor transfer logic that a complete descriptor has been loaded into the CFIFO by the CPU and causes the descriptor transfer logic to take over management of the descriptor from the CPU and initiate the transaction for the descriptor currently in the CFIFO and associate subsequently loaded data in the CFIFO with a new descriptor.

4. The apparatus according to claim 3 wherein the descriptor transfer logic includes multiple channel buffers coupled between the CFIFO and the interconnect, wherein the channel buffers are configured to send out commands from the CFIFO, and the descriptor transfer logic is configured to generate a stall signal to the CPU preventing the CPU from writing to the send register when all of the channel buffers are busy.

5. The apparatus according to claim 3 wherein the send register includes a resource Id field identifying the resources targeted for the transaction associated with the descriptor in the CFIFO, a count field identifying an amount of buffer space the descriptor transfer logic should allocate to the transaction associated with the descriptor loaded in the CFIFO, and an acknowledge field indicating an amount of data the descriptor transfer logic should monitor for the transaction associated with the descriptor loaded in the CFIFO.

6. The apparatus according to claim 2 including a response buffer coupled between the CPU and the interconnect and having multiple regions each allocated to different transactions by the descriptor transfer logic independently of the CPU.

7. The apparatus according to claim 6 wherein the descriptor transfer logic generates a stall signal preventing the CPU from writing to the send register when the CPU tries to initiate a new transaction while all of the regions in the response buffer are already allocated.

11. The apparatus according to claim 2 wherein the description transfer logic includes control logic configured to generate handles associated with the descriptors in the CFIFO.

12. The apparatus according to claim 11 wherein the control logic is configured to assign a unique transaction identifier for each handle, allocate a region of a response buffer located in the descriptor transfer logic to the transaction, and identify the allocated region in the handle.

13. The apparatus according to claim 12 wherein the control logic is configured to compare a first handle currently being referenced by the CPU with a second handle currently associated with a region in the response buffer referenced by the first handle, and conditionally execute operations according to the comparison between the first and second handle.

14. The apparatus according to claim 11 wherein the descriptor transfer logic includes a wait register that when written to by the CPU causes the control logic to stall the CPU.

15. The apparatus according to claim 14 wherein the descriptor transfer logic includes a release register configured to reserve a region in the response buffer and further configured to release that region in the response buffer.

16. The apparatus according to claim 1 including multiple different independently operating descriptor transfer logic each configured to independently manage transactions for different threads operated by the processing element.

8. A method comprising:

receiving descriptors with descriptor transfer logic, wherein the descriptors are generated by a programmable Central Processing Unit (CPU) and the descriptor transfer logic is located between the CPU and resources and the resources are other processors or memory used by the CPU for processing data;

managing a transaction for the CPU with the descriptor transfer logic, wherein the transaction includes the descriptor transfer logic sending the descriptors to the resources for execution;

receiving with the descriptor transfer logic responses back from the resources in response to the sent descriptors;

managing allocation and operation of buffers and registers that initiate the transaction, track the status of the transaction, and receive the responses back from the resources with the descriptor transfer logic independently of the CPU; and

providing the responses to the CPU for further processing.

9. The method according to claim 8 further comprising:

buffering multiple different batched resource instructions contained in the same or multiple different descriptors received from the CPU in a First In-First Out Buffer (FIFO) within the descriptor transfer logic, wherein the FIFO has an input coupled to the CPU and an output coupled through an interconnect to the resources;

monitoring for write operations from the CPU to a send register in the descriptor transfer logic;

initiating transfer of the batched resource instructions with the descriptor transfer logic responsive to the CPU writing to the send register; and

managing the transfer of the batched resource instructions from the FIFO to the resources with the descriptor transfer logic.

10. The method according to claim 8 further comprising:

receiving multiple different threads each independently operating different descriptor transfer logic, the different descriptor transfer logic each coupled between the CPU and the resources and each comprising separate command buffers, send registers, response buffers, and control logic configured to separately manage the transfer of commands to the resources and manage the receiving of associated responses data back from the resources.

20. The method according to claim 8 further comprising:

writing data into a send register;

generating a unique handle identifier for the transaction according to data in the send register;

identifying and allocating a region of a response buffer to the transaction;

storing a pointer in the handle pointing to the region of the response buffer allocated to the transaction;

storing the handle in a select register for subsequent referencing by the CPU;

monitoring the CPU for access to the region of the response buffer; and

releasing the handle and the region of the response buffer after being accessed by the CPU.

17. An apparatus, comprising:

a general purpose programmable processor core;

resources comprising multiple different computer or co-processing elements configured to perform operations responsive to commands contained in descriptors generated by the processor core;

descriptor transfer logic coupled between the processor core and through an interconnect to the resources, wherein the descriptor transfer logic includes;

a command buffer configured to buffer the descriptors generated by the processor core;

a send register configured to control management of the descriptors in the send register, initiation of associated transactions, and management of buffer transaction parameters associated with the descriptors;

a response buffer configured to storage response data associated with the transactions; and

control logic configured to manage handles for each of the transactions that include different fields that each contain different status information for the transactions, wherein the handles are stored in handle registers and read by the processor core to determine the status information for the transactions.

18. The apparatus according to claim 17 wherein each of the handles includes:

an identifier field containing a value uniquely identifying an associated transaction;

a pointer field containing a pointer value to a region in the response buffer where data from the associated transaction is stored; and

a wait field containing a value for stalling the processor core.

19. The apparatus according to claim 17 wherein the send register includes:

a resource Id field identifying the resources;

a response count field configured to manage an amount of total response data associated with the transactions, and

an acknowledge count field configured to manage an amount data associated with the transactions.