ATA HDD interface for personal media player with increased data transfer throughput

• US 7,739,440 B2
• Filed: 08/16/2007
• Issued: 06/15/2010
• Est. Priority Date: 08/16/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Zhu, Xiaoming
• Primary Examiner(s): Tsai; Henry W. H.
• Assistant Examiner(s): Snyder; Steven G
• Application Number:
  US11/839,880
• Publication Number:
  US 20090049209A1
• Time in Patent Office: 1,034 Days
• Field of Search: 710/23, 710/62, 710/72, 710/74, 710/305, 710/313, 710/315, 370/465, 370/466, 370/467, 713/501, 713/502
• US Class Current: 710/305
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

This invention is a method allowing for interfacing high speed hard disk drives (ATA-HDD) in high throughput PIO modes to currently available digital media processors (DMP). The prescribed interface programs signals available in the DMP external memory interface (EMIF) functions to match the requirements of ATA-HDD PIO functions. Selected signal redefinition and minimal glue logic is employed to form a seamless link between the EMIF I/O of the digital media processor DMP and the ATA-HDD hard drive.

Claims

1. A digital device comprising:

a digital media player having a programmable external memory interface, said programmable external memory interface including;

an address valid output line,

five address bit output lines,

a chip enable output line,

a write/read output line,

an output enable output line,

a wait request input line,

an interrupt input line, and

a plurality of data lines;

a first OR gate having a first input connected to said chip enable output line, a second input connected to write/read output line and an output;

a second OR gate having a first input connected to said chip enable output line, a second input connected to said output enable output line and an output;

an Advanced Technology Attachment/Integrated Drive Electronics (ATA/IDE) hard drive including;

an address valid input line connected to said address valid output line,

three address input lines connected to corresponding ones of three least significant bits of said address output lines,

a first chip select input line connected to a next most significant one of said address output lines,

a second chip select input line connected to a most significant one of said address output lines,

a write duration input signal line connected to said output of said first OR gate,

a read duration input signal line connected to said output of said second OR gate,

a wait request output line connected to said wait request input line,

an interrupt output line connected to said interrupt input line, and

a plurality of data lines, each data line connected to a corresponding data line of said external memory interface.

2. The digital device of claim 1, wherein:

said ATA/IDE hard drive is operable in a selected one of a plurality of operating modes having corresponding rates of operation; and

said digital media player programs said programmable external memory interface to supply signals to said ATA/IDE hard drive corresponding to said selected operating mode.

3. The digital device of claim 2, wherein:

said ATA/IDE hard drive is operable in a programmable I/O-4 mode having a rate of operation of 16.6 Mbytes/second; and

said digital media player programs said programmable external memory interface for read operation to

supply a high output at said address valid output line for 120 nsec,

supply a low output at said chip enable output line having a duration of 100 nsec,

supply a high output at said write/read output line and a high output at said output enable output for a duration of 30 nsec,

supply a low output at said write/read output line and a low output at said output enable output line for a duration of 70 nsec,

supply valid address signals on said plurality of address output lines for at least 20 nsec before an end of said supply of said low output at said write/read output line and said low output at said output enable output line until at least 10 nsec after an end of said supply of said low output at said write/read output line and said low output at said output enable output line, and

receive data on said data lines before said end of said supply of said low output at said write/read output line and said low output at said output enable output line.

4. The digital device of claim 2, wherein:

said ATA/IDE hard drive is operable in a programmable IO-4 mode having a rate of operation of 16.6 Mbytes/second; and

said digital media player programs said programmable external memory interface for write operation to

supply a high output at said address valid output line for 120 nsec,

supply a low output at said chip enable output line having a duration of 100 nsec,

supply a high output at said write/read output line and a high output at said output enable output for a duration of 30 nsec,

supply a low output at said write/read output line and a low output at said output enable output line for a duration of 70 nsec,

supply valid address signals on said plurality of address output lines for at least 20 nsec before an end of said supply of said low output at said write/read output line and said low output at said output enable output line until at least 10 nsec after an end of said supply of said low output at said write/read output line and said low output at said output enable output line, and

supply data on said data lines from at least 20 nsec before an end of said supply of said low output at said write/read output line and said low output at said output enable output line until at least 10 nsec after an end of said supply of said low output at said write/read output line and said low output at said output enable output line.