High-performance, superscalar-based computer system with out-of-order instruction execution

• US 7,739,482 B2
• Filed: 12/21/2006
• Issued: 06/15/2010
• Est. Priority Date: 07/08/1991
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Wang, Johannes, Wang, Sze-Shun, Nguyen, Le Trong, Miyayama, Yoshiyuki, Trang, Quang H., Lau, Te-Li, Garg, Sanjiv, Lentz, Derek J., Hagiwara, Yasuaki
• Primary Examiner(s): Li; Aimee J
• Application Number:
  US11/642,599
• Publication Number:
  US 20070106878A1
• Time in Patent Office: 1,272 Days
• Field of Search: 712/23, 712/41, 712/205, 712/214, 712/215, 712/216, 712/217, 712/220
• US Class Current: 712/23
• CPC Class Codes: G06F 9/30061 Multi-way branch instructions, e.g. CASE
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/327 for interrupts
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 : Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 : using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3865 : using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Claims

1. A superscalar microprocessor comprising:

a prefetch unit to prefetch a plurality of instructions from a memory in a predetermined program order;

a buffer placed subsequent to said prefetch unit to buffer said prefetched instructions, wherein the prefetched instructions are arranged in least two groups of instructions in the buffer;

a decoder to decode two or more instructions among said buffered instructions simultaneously;

a plurality of functional units to execute instructions simultaneously;

a register file used by the functional units in executing decoded instructions, said register file comprising a plurality of registers for storing out of order execution results, said registers being arranged in a plurality of groups, wherein a register used for storing a result of a particular instruction is determined by a position of that instruction in the buffer, and a mechanism to avoid two or more of said functional units simultaneously referring to a same one of said registers when executing instructions simultaneously;

a dependency check unit to determine a dependency among said decoded instructions in at least two groups of instructions from the buffer based on service conditions of said register and at least one flag of a processor state register; and

a dispatch circuit to allocate out of order execution of said decoded instructions when said dependency check unit determines that there is no dependency among said decoded instructions, wherein the dispatch circuit is capable of allocating instructions from different groups for simultaneous execution.

2. A superscalar microprocessor comprising, on a single silicon chip:

a prefetch unit that prefetches a plurality of instructions from an external memory in a predetermined program order;

a buffer unit provided downstream of the prefetch unit, said buffer unit being provided to hold a plurality of instructions, wherein the plurality of instructions is arranged in at least two groups of instructions;

a decoder unit provided downstream of the buffer unit, said decoder unit being provided to decode a plurality of instructions concurrently among the instructions held by the buffer;

a plurality of functional units capable of executing instructions concurrently;

a register file unit that has a plurality of registers which are used at the time of execution of decoded instructions by the functional units, said register file unit further having a plurality of temporary buffers for storing results of out-of-order execution of a plurality of instructions;

a dependency checking unit that detects a dependency among the plurality of instructions decoded by the decoder unit based on at least use condition of the registers;

an instruction issuing unit that issues an instruction, determined by the dependency checking unit to have no constraint on execution based on a dependency, for out-of-order execution to the plurality of functional units, wherein the instruction issuing unit is capable of issuing instructions from different groups concurrently; and

a retiring unit that retires a group of instructions together, wherein, when retiring an instruction executed out of order, the retiring unit sets transfers an execution result from one of the temporary buffers to be one of the plurality of registers, and releases the one of the temporary buffers.

3. The superscalar microprocessor of claim 2, wherein the buffer unit comprises a FIFO buffer.

4. The superscalar microprocessor of claim 2, wherein each group of instructions includes up to four instructions and the buffer unit is capable of providing more than four instructions to the decoder unit.

5. The superscalar microprocessor of claim 2, wherein the instruction issuing unit is capable of issuing up to four instructions concurrently to the plurality of functional units.

6. The superscalar microprocessor of claim 2, wherein the buffer unit includes a plurality of instruction registers and each of the instruction registers has a capacity to store a group of instructions consisting of up to four instructions.

7. The superscalar microprocessor of claim 2, wherein the prefetch unit prefetches the instructions from a cache.

8. A superscalar microprocessor for executing instructions fetched from an instruction store, the superscalar microprocessor comprising:

an instruction buffer for buffering a plurality of instructions;

a split decoder coupled to a portion of the instruction buffer, the split decoder for detecting a branch instruction;

a second buffer retaining a plurality of instructions placed after the split decoder, the second buffer being arranged such that the plurality of instructions are retained in a plurality of groups of instructions;

a second decoder for concurrently decoding a plurality of instructions buffered in the second buffer;

a dispatch means for concurrently dispatching a plurality of instructions buffered in the second buffer after concurrently decoding by the second decoder; and

an execution unit, comprising;

a plurality of functional units for executing a plurality of instructions dispatched from the dispatch means in an out of program order fashion;

a register file for storing execution results from a plurality of the functional units, the register file having a plurality of temporary buffers for storing execution results of instructions executed in an out of program order fashion, the temporary buffers being arranged in a plurality of groups corresponding to the arrangement of the second buffer, wherein a result of executing an instruction dispatched from the second buffer is stored in a temporary buffer corresponding to the location of the instruction in the second buffer; and

a data routing path, wherein the register file communicates with the functional units via the data routing path to provide the data to the functional units.

9. The superscalar microprocessor of claim 8, wherein the instruction buffer comprises a FIFO buffer.

10. The superscalar microprocessor of claim 8, wherein the second buffer is arranged such that each group of instructions consists of up to four instructions and wherein the second buffer is capable of providing more than four instructions to the dispatch means.

11. The superscalar microprocessor of claim 8, wherein the dispatch means is capable of dispatching up to four instructions to the execution unit concurrently.

12. The superscalar microprocessor of claim 8, wherein instructions are provided to the instruction buffer from a cache.

13. A data processing system comprising a microprocessor according to claim 8 and external memory.

14. A superscalar microprocessor comprising:

a prefetch unit that prefetches an instruction group having a plurality of instructions from a memory according to a predetermined program order;

a buffer disposed at a latter stage of said prefetch unit, said buffer having a plurality of entries, each entry for buffering one of a plurality of instruction groups;

a decoder disposed at a latter stage of said buffer, said decoder for simultaneously decoding a plurality of instructions that are included in at least one instruction group;

a plurality of functional units that execute instructions concurrently;

a register file equipped with a register array having a plurality of registers that are used when executing decoded instructions by said functional units, said plurality of registers including a plurality of temporary buffers arranged in a plurality of groups of temporary buffers and a register array;

a dependency relation check unit that detects a dependency relation among said plurality of instructions decoded by said decoder, on the basis of use conditions of at least said register array,

an instruction issuance unit that allocates an instruction judged to have no dependency relation by said dependency relation check unit to said plurality of functional units to execute, wherein at least one of the plurality of instructions decoded by the decoder is executed out of the predetermined program order; and

a retirement unit that retires instruction groups from the buffer, wherein, when the plurality of instructions included in an instruction group retired together, the entry of said buffer which corresponds to the instruction group is released.

15. A data processing apparatus comprising:

the superscalar microprocessor according to claim 14, and

a memory from which the superscalar microprocessor accesses data through a system memory bus.

16. The superscalar microprocessor according to claim 14, wherein when said retirement unit retires an instruction group from the buffer, said retirement unit also copies content of the register file from a group of said temporary buffers to registers in said register array.

17. A data processing apparatus comprising:

a superscalar microprocessor according to claim 16; and

a memory from which the superscalar microprocessor accesses data through a system memory bus.

18. The superscalar microprocessor of claim 14, wherein the superscalar microprocessor is RISC-based.