Method and mechanism for implementing electronic designs having power information specifications background

• US 7,739,629 B2
• Filed: 10/30/2006
• Issued: 06/15/2010
• Est. Priority Date: 04/14/2006
• Status: Expired

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Gallagher, Patrick, Sharp, Steven, Chu, Christina, Gupta, Ankur, Chickermane, Vivek, Wang, Qi, Bhatia, Sandeep, Chen, Pinhong, Chen, Yonghao, Pandey, Manish, Tsai, Huan-Chih
• Primary Examiner(s): Kik; Phallaka
• Application Number:
  US11/590,657
• Publication Number:
  US 20070245285A1
• Time in Patent Office: 1,324 Days
• Field of Search: 716/2, 716/4, 716/7, 703/14
• US Class Current: 716/136
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

Claims

1. A method of adding power control circuitry to an RTL circuit design comprising:

using a computer to demarcate multiple power domains within the circuit design;

wherein demarcating respective power domains includes designating design object instances within the circuit design encompassed within respective power domains;

specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and

defining isolation behavior relative to respective power domains.

2. The method of claim 1,

wherein demarcating respective power domains includes designating design object instances within the circuit design encompassed within respective power domains;

and

wherein at least one power domain encompasses at least one other power domain.

3. The method of claim 1, wherein demarcating a respective power domain includes identifying a ground net that connects with a switch that controls shut off of the respective power domain.

4. The method of claim 1, wherein demarcating a respective power domain includes identifying a power net that connects with a switch that controls shut off the respective power domain.

5. The method of claim 1, wherein demarcating a respective power domain includes setting forth a respective expression representing a condition upon which the respective demarcated power domain is to be shut off.

6. The method of claim 1 further including designating a sequencing of the power modes.

7. The method of claim 1, wherein defining isolation behavior includes designating whether isolation behavior is to apply to input pins of a respective power domain.

8. The method of claim 1, wherein defining isolation behavior includes designating whether isolation behavior is to apply to output pins of a respective power domain.

9. The method of claim 1, wherein defining isolation behavior includes designating values of respective pins of a respective power domain during an isolation state while the respective power domain is turned off.

10. The method of claim 1,

wherein defining isolation behavior includes designating values of respective pins of a respective power domain during an isolation state while the respective power domain is turned off;

and

wherein the output value is one of high, low or at a level equal to its level prior to activation of the isolation state.

11. The method of claim 1 further including designating the power domain in which logic to implement the isolation behavior.

12. The method of claim 1,

wherein defining isolation behavior relative to respective power domains includes defining isolation behavior between a first demarcated power domain and a second demarcated power domain;

and further including;

designating whether to implement isolation behavior logic in the first demarcated power domain or in the second demarcated power domain.

13. The method of claim 1 further including designating state retention behavior during shut off of at least one demarcated power domain.

14. The method of claim 1 further including:

designating state retention behavior during shut off of at least one demarcated power domain;

wherein designating state retention behavior includes designating at least one class of library cells eligible to implement state retention logic.

15. The method of claim 1 further including:

designating state retention behavior during shut off of at least one demarcated power domain;

wherein designating state retention behavior includes designating a power domain in which to replace a storage cell with state retention logic to implement state retention behavior during shut off of at least one demarcated power domain.

16. The method of claim 1 further including:

designating state retention behavior during shut off of at least one demarcated power domain;

wherein designating state retention behavior includes setting forth an expression to representing a condition upon which to store a state to be retained during shut off of the at least one demarcated power domain.

17. The method of claim 1 further including:

designating state retention behavior during shut off of at least one demarcated power domain;

wherein designating state retention behavior includes setting forth an expression to representing a condition upon which to restore a state retained during shut off of the at least one demarcated power domain.

18. The method of claim 1 further including designating level shifting behavior between a first demarcated power domain and a second demarcated power domain.

19. An article of manufacture that includes a computer data storage device, encoded with code structure, when executed by a computer causes the computer data storage device, to implement a method comprising:

using a computer to instruct a circuit design process to include power control behavior in a circuit design at each of an RTL and a netlist level, the behavior including;

multiple power domains demarcated by design objects of the circuit design; and

multiple power modes each power mode including a different combination of on/off states of the multiple demarcated power domains.

20. The article of manufacture of claim 19 said method further include a step of setting forth a respective expression representing a condition upon which the respective demarcated power domain is to be shut off.

21. The article of manufacture of claim 19 further including code defining isolation behavior relative to respective power domains.

22. The article of manufacture of claim 19 said method further include a step of designating a sequencing of the power modes.

23. The article of manufacture of claim 19 said method further include a step of designating state retention behavior during shut off of at least one demarcated power domain.

24. The article of manufacture of claim 19 said method further include a step of designating level shifting behavior between a first demarcated power domain and a second demarcated power domain.

25. A method of designing power control circuitry for an RTL circuit design comprising:

using a computer to produce a power specification encoded in computer readable medium that specifies;

multiple power domains demarcated by design objects of the circuit designs, and

multiple power modes each power mode including a different combination of on/off states of the multiple demarcated power domains;

using the power specification to simulate power-related behavior of an RTL version of the circuit design; and

using the power specification to place power-related cells of a netlist version of the circuit design.

26. A method of designing power control circuitry for an integrated circuit design at each of an RTL and a netlist level comprising:

using a computer to produce a power specification encoded in computer readable medium that specifies;

multiple power domains demarcated by design objects of the RTL circuit design, and

multiple power modes each power mode including a different combination of on/off states of the multiple demarcated power domains;

using the power specification to synthesize power-related logic of the circuit design; and

using the power specification to place power-related cells of a netlist version of the circuit design.

27. The method of claim 26 further including using the power specification to simulate power-related behavior of an RTL version of the circuit design.

28. A method of designing power control circuitry for an integrated circuit design at each of an RTL and a netlist level comprising:

using a computer to produce a power specification encoded in computer readable medium that specifies;

multiple power domains demarcated by design objects of the RTL circuit design, and

multiple power modes each power mode including a different combination of on/off states of the multiple demarcated power domains;

using the power specification to place power-related cells of a netlist version of the circuit design; and

using the power specification to generate test signal patterns to test operation of the circuit design.

29. The method of claim 28 further including:

using the power specification to simulate power-related behavior of an RTL version of the circuit design; and

using the power specification to synthesize power-related logic of the circuit design.