Method and apparatus transporting charges in semiconductor device and semiconductor memory device

• US 7,741,177 B2
• Filed: 07/16/2007
• Issued: 06/22/2010
• Est. Priority Date: 06/06/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Chih-Hsin Wang
• Inventors: Wang, Chih-Hsin
• Primary Examiner(s): Nguyen; Dao H
• Application Number:
  US11/879,179
• Publication Number:
  US 20070281426A1
• Time in Patent Office: 1,072 Days
• Field of Search: 438/211, 438/257, 438/259, 438/261, 438/513, 257/314, 257/315, 257/316, 257/324, 257/E21.17, 257/E21.68, 257/E21.585, 257/E27.103, 365/185.18
• US Class Current: 438/257
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of providing a memory cell comprises providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions; arranging a first insulator layer adjacent to the substrate; arranging a charge storage region adjacent to the first insulator layer; arranging a second insulator layer adjacent to the charge storage region; arranging a first conductive region adjacent to the second insulator layer; arranging a layer adjacent to the first conductive region; arranging a second conductive region adjacent to the layer; and increasing mechanical stress of at least one of the first and second conductive regions. The second conductive region overlaps the first conductive region at an overlap surface, and wherein a line perpendicular to the overlap surface intersects at least a portion of the charge storage region.

Claims

1. A method of forming a memory cell, the method comprising:

forming a body of a first conductivity type in a semiconductor substrate;

forming a first insulator layer adjacent to the substrate;

forming a charge storage region adjacent to the first insulator layer;

forming first and second regions of a second conductivity type in the body;

forming a channel region in the body between the first region and the second region, and generally disposed adjacent to and insulated from the charge storage region;

forming a second insulator layer adjacent to the charge storage region;

forming a first electrically conductive region comprising at least a portion thereof disposed adjacent to and insulated from the charge storage region by the second insulator layer;

forming a layer adjacent to the first electrically conductive region;

forming a second electrically conductive region adjacent to and separated from the first electrically conductive region by the layer; and

forming a strain source that provides mechanical stress to at least one of the first and second electrically conductive regions,

wherein;

the second electrically conductive region overlaps the first electrically conductive region at an overlap surface; and

a line perpendicular to the overlap surface intersects at least a portion of the charge storage region.

2. The method of claim 1, wherein at least a portion of the charge storage region is disposed under the overlap surface.

3. The method of claim 1, wherein the strain source comprises a material selected from the group consisting of thermal-CVD nitride, plasma-CVD nitride, tungsten-silicide, amorphous silicon, poly SiGe, TaN, and TiN.

4. The method of claim 1, wherein the strain source imposes a compressive stress.

5. The method of claim 1, wherein the strain source imposes a tensile stress.

6. The method of claim 1, further comprising ion implanting one or more impurities into the strain source for tailoring a stress level of the mechanical stress.

7. The method of claim 1, wherein the strain source comprises dislocation loops in at least one of the first and second electrically conductive regions.

8. The method of claim 1, further comprising ion implanting atoms at a predetermined dosage into at least one of the first and second electrically conductive regions.

9. The method of claim 1, wherein the atoms comprise at least one material selected from the group consisting of Si, Ge, As, and nitrogen.

10. The method of claim 1, wherein:

the layer comprises a filter;

the filter includes a multi-layer dielectric and further comprises a voltage-divider function for reducing voltage drops in the multi-layer dielectric; and

the filter provides a filtering function selected from a group consisting of band-pass filtering, mass-filtering, and charge-filtering.

11. The method of claim 10, wherein:

the layer comprises a filter; and

the filter provides a filtering function selected from a group consisting of band-pass filtering, mass-filtering, and charge-filtering.

12. The method of claim 1, wherein the forming the layer comprises:

forming a first dielectric adjacent to the second electrically conductive region; and

forming a second dielectric adjacent to the first dielectric, wherein the second dielectric has an energy band gap narrower than an energy band gap of the first dielectric.

13. The method of claim 12, wherein a product of a dielectric constant of the second dielectric and a thickness of the first dielectric is substantially greater than a product of a dielectric constant of the first dielectric and a thickness of the second dielectric.

14. The method of claim 12, wherein the first dielectric comprises oxide, and the second dielectric comprises a material selected from the group consisting of nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

15. The method of claim 14, wherein the oxide is formed using at least one technique selected from the group consisting of thermal oxidation, HTO, TEOS, and ISSG.

16. The method of claim 12, wherein the first dielectric comprises oxynitride, and the second dielectric comprises a material selected from the group consisting of nitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

17. The method of claim 12, wherein the second dielectric is arranged between the first dielectric and the second electrically conductive region.

18. The method of claim 12, wherein the first dielectric and the second dielectric are arranged between said second electrically conductive region and one of a drain and a source.

19. The method of claim 1, wherein the charge storage region comprises a plurality of spaced-apart nano-particles.

20. The method of claim 1, wherein the charge storage region comprises a trapping dielectric comprising a plurality of trapping centers.

21. The method of claim 1, wherein the forming the first and second regions is performed before the forming the first insulator layer adjacent to the substrate.

22. The method of claim 1, wherein the forming the first and second regions is performed after the forming the charge storage region adjacent to the first insulator.

23. The method of claim 1, further comprising arranging the strain source adjacent to a first surface of the second electrically conductive region,

wherein:

the strain source adjusts the mechanical stress including one of tensile stress and compressive stress of at least one of the second electrically conductive region and the first electrically conductive region;

the layer is adjacent a second surface of the second electrically conductive region; and

the first surface opposes the second surface.

24. The method of claim 23, wherein the strain source provides a piezo-effect in at least one of the first electrically conductive region and the second electrically conductive region.

25. The method of claim 23, wherein:

the strain source is fabricated using chemical-vapor-deposition; and

the strain source comprises nitride.

26. The method of claim 23, wherein:

the strain source is arranged adjacent to the first surface of the second electrically conductive region and adjacent to a tunneling dielectric; and

the tunneling dielectric is arranged between the second electrically conductive region and a blocking dielectric.

27. The method of claim 23, wherein:

the first insulator layer is a channel dielectric;

the charge storage region is a floating gate;

the first and second regions include a source and a drain;

the second insulator layer is a retention dielectric;

the first electrically conductive region is a ballistic gate;

the layer comprises a plurality of dielectrics; and

the second electrically conductive region is a tunneling gate.

28. The method of claim 1, wherein:

the layer comprises a filter; and

the method further comprises controlling flow of charge carriers of one polarity through the filter in a first direction using a first set of electrically alterable potential barriers of the layer.

29. The method of claim 28, further comprising controlling flow of charge carriers of an opposite polarity through the layer in a second direction using a second set of electrically alterable potential barriers,

wherein the second direction is substantially opposite to the first direction.

30. The method of claim 28, further comprising applying an electric field to alter height of at least one of said electrically alterable potential barriers.

31. A method of providing an array of memory cells, the method comprising:

forming a body of a first conductivity type in a semiconductor substrate;

forming a first insulator layer adjacent to the substrate;

forming a plurality of charge storage regions adjacent to the first insulator layer and arranged in an array of columns extending in a first direction and rows in a second direction generally perpendicular to the first direction;

forming a plurality of first regions of a second conductivity type;

forming a plurality of second regions of the second conductivity type;

forming a plurality of channel regions in the body each extending between one of the first regions and one of the second regions, and generally disposed adjacent to and insulated from one of the charge storage regions;

forming a second insulator layer adjacent to each of the charge storage regions;

forming a plurality of first electrically conductive regions each comprising at least a portion thereof disposed adjacent to and insulated from one of the charge storage regions by the second insulator layer;

forming a plurality of layers each comprising at least a portion disposed adjacent to one of the first electrically conductive regions;

forming a plurality of second electrically conductive regions each comprising charge carriers with an energy distribution and each disposed adjacent to and separated from one of the first electrically conductive regions by one of the layers;

forming a plurality of parallel spaced apart bit-lines extending in the first direction with at least one of the bit-lines electrically connected to at least one of the second regions; and

forming a plurality of strain sources, each strain source providing a mechanical stress to at least one of the first and second electrically conductive regions,

wherein;

each of the first electrically conductive regions overlaps one of the second electrically conductive regions at an overlap surface; and

lines perpendicular to the overlap surfaces intersect corresponding ones of the charge storage regions.

32. The method of claim 31, wherein each of the strain sources comprises a material selected from the group consisting of thermal-CVD nitride, plasma-CVD nitride, tungsten-silicide, amorphous silicon, poly SiGe, TaN, and TiN.

33. The method of claim 31, wherein each of the strain sources imposes a compressive stress.

34. The method of claim 31, wherein each of the strain sources imposes a tensile stress.

35. The method of claim 31, further comprising:

forming a plurality of parallel spaced apart word-lines of conductive material each extending across the bit-lines in the second direction, wherein each of the word-lines is electrically connected to at least one of the first electrically conductive regions; and

forming a plurality of parallel spaced apart tunneling-lines of conductive material each extending in the first direction and electrically connected to at least one of the second electrically conductive regions.

36. The method of claim 35, further comprising forming a plurality of oxide line blocks interlaced with the word-lines.

37. The method of claim 31, wherein the at least a portion of each of charge storage regions is disposed under a corresponding one of the overlap surfaces.

38. The method of claim 31, wherein each of the bit-lines is formed in at least a portion of the body.

39. The method of claim 31, wherein at least one of the bit-lines is electrically connected to at least one of the first regions.

40. The method of claim 31, wherein each of the plurality of layers comprises a filter.

41. The method of claim 31, wherein each of the filters includes a multi-layer dielectric and further comprises a voltage-divider function for reducing voltage drops in the multi-layer dielectric.

42. The method of claim 31, wherein each of the filters includes at least one filtering function selected from a group consisting of band-pass filtering, mass-filtering, and charge-filtering.

43. The method of claim 31, wherein the forming the plurality of layers comprises:

forming a plurality of first dielectrics each adjacent to one of the second electrically conductive regions; and

forming a plurality of second dielectrics each adjacent to one of the first dielectrics, wherein each of the second dielectrics has an energy band gap narrower than an energy band gap of each of the first dielectrics.

44. The method of claim 43, wherein a product of a dielectric constant of each of the second dielectrics and a thickness of each of the first dielectrics is substantially greater than a product of a dielectric constant of each of the first dielectrics and a thickness of each of the second dielectrics.

45. The method of claim 43, wherein each of the first dielectrics comprises oxide, and each of the second dielectrics comprises a material selected from the group consisting of nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

46. The method of claim 43, wherein each of the first dielectrics comprises oxynitride, and each of the second dielectrics comprises a material selected from the group consisting of nitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

47. The method of claim 31, wherein the forming the plurality of first and second regions is performed before the forming the first insulator layer adjacent to the substrate.

48. The method of claim 31, wherein the forming the plurality of first and second regions is performed after the forming the plurality of charge storage region adjacent to the first insulator.

49. A method of providing a memory cell, the method comprising:

providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions;

arranging a first insulator layer adjacent to the substrate;

arranging a charge storage region adjacent to the first insulator layer;

arranging a second insulator layer adjacent to the charge storage region;

arranging a first conductive region adjacent to the second insulator layer;

arranging a layer adjacent to the first conductive region;

arranging a second conductive region adjacent to and separated from the first conductive region by the layer; and

increasing mechanical stress of at least one of the first and second conductive regions,

wherein;

the second conductive region overlaps the first conductive region at an overlap surface; and

a line perpendicular to the overlap surface intersects at least a portion of the charge storage region.

50. The method of claim 49, wherein the at least a portion of the charge storage region is disposed under the overlap surface.

51. The method of claim 49, wherein increasing mechanical stress comprises providing a material selected from the group consisting of thermal-CVD nitride, plasma-CVD nitride, tungsten-suicide, amorphous silicon, poly SiGe, TaN, and TiN.

52. The method of claim 51, further comprising ion implanting an impurity into the material.

53. The method of claim 49, wherein the mechanical stress comprises compressive stress.

54. The method of claim 49, wherein the mechanical stress comprises tensile stress.

55. The method of claim 49, further comprising providing dislocation loops in at least one of the first and second conductive regions.

56. The method of claim 49, further comprising ion implanting atoms at a predetermined dosage into at least one of the first and second conductive regions.

57. The method of claim 56, wherein the atoms comprise at least one material selected from the group consisting of Si, Ge, As, and nitrogen.

58. The method of claim 49, wherein the layer comprises a filter.

59. The method of claim 58, wherein the filter includes a multi-layer dielectric.

60. The method of claim 58, further comprising performing at least one of band-pass filtering, mass-filtering, and charge-filtering using the filter.

61. The method of claim 49, wherein arranging the layer comprises:

forming a first dielectric adjacent to the second conductive region; and

forming a second dielectric adjacent to the first dielectric, wherein the second dielectric has an energy band gap narrower than an energy band gap of the first dielectric.

62. The method of claim 61, wherein a first product of a dielectric constant of the second dielectric and a thickness of the first dielectric is substantially greater than a second product of a dielectric constant of the first dielectric and a thickness of the second dielectric.

63. The method of claim 61, wherein the first dielectric comprises oxide, and the second dielectric comprises a material selected from the group consisting of nitride, oxynitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

64. The method of claim 63, wherein the oxide is formed using at least one technique selected from the group consisting of thermal oxidation, HTO, TEOS, and ISSG.

65. The method of claim 61, wherein the first dielectric comprises oxynitride, and the second dielectric comprises a material selected from the group consisting of nitride, Al₂O₃, HfO₂, TiO₂, ZrO₂, Ta₂O₅, and alloys formed thereof.

66. The method of claim 49, wherein the charge storage region comprises a plurality of spaced-apart nano-particles.

67. The method of claim 49, wherein the charge storage region comprises a trapping dielectric comprising a plurality of trapping centers.

68. A method of providing a memory cell, the method comprising:

providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions;

forming a first insulator layer adjacent to the substrate;

forming a charge storage region adjacent to the first insulator layer;

forming a second insulator layer adjacent to the charge storage region;

forming a first conductive region adjacent to the second insulator layer;

forming a layer adjacent to the first conductive region;

forming a second conductive region adjacent to and separated from the first conductive region by the layer; and

increasing mechanical stress of at least one of the first and second conductive regions,

wherein;

the second conductive region overlaps the first conductive region at an overlap surface; and

a line perpendicular to the overlap surface intersects at least a portion of the charge storage region.