Metal line of semiconductor device and method for forming the same

• US 7,741,216 B2
• Filed: 12/02/2008
• Issued: 06/22/2010
• Est. Priority Date: 01/02/2008
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Jung, Dong Ha, Yeom, Seung Jin, Kim, Jeong Tae, Kim, Baek Mann
• Primary Examiner(s): Smith; Matthew
• Assistant Examiner(s): Swanson; Walter H
• Application Number:
  US12/326,374
• Publication Number:
  US 20090166870A1
• Time in Patent Office: 567 Days
• Field of Search: 257/751, 257/E21.495, 257/E21.141, 438/643
• US Class Current: 438/643
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and having a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier has a multi-layered structure of a V layer, a V_xN_y layer and a V_xN_yO_z layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Claims

1. A metal line of a semiconductor device, comprising:

an insulation layer formed on a semiconductor substrate and having a metal line forming region;

a diffusion barrier formed on a surface of the metal line forming region of the insulation layer and having a multi-layered structure comprising a V layer, a V_xN_y layer and a V_xN_yO_z layer, wherein the V layer, the V_xN_y layer and the V_xN_yO_z layer are formed on a surface of the insulation layer in sequence; and

a metal layer formed on the diffusion barrier in the metal line forming region of the insulation layer.

2. The metal line according to claim 1, wherein the V layer has a thickness in the range of 10˜

100 Å

.

3. The metal line according to claim 1, wherein the V_xN_y layer has a thickness in the range of 5˜

50 Å

.

4. The metal line according to claim 1, wherein, in the V_xN_y layer, x has a range of 0.8˜

0.95 and y has a range of 0.05˜

0.2.

5. The metal line according to claim 1, wherein the V_xN_yO_z layer has a thickness in the range of 5˜

50 Å

.

6. The metal line according to claim 1, wherein, in the V_xN_yO_z layer, x has a range of 0.7˜

0.94 and y has a range of 0.05˜

0.2.

7. The metal line according to claim 1, wherein the metal layer comprises a copper layer, and the metal layer fills the metal line forming region.

8. A method for forming a metal line of a semiconductor device, comprising the steps of:

forming an insulation layer having a metal line forming region on a semiconductor substrate;

forming a V layer on the insulation layer and the surface of the metal line forming region;

forming a V_xN_y layer on the V layer;

forming a V_xN_yO_z layer by oxidating a surface of the V_xN_y layer, so that a diffusion barrier having a multi-layered structure of the V layer, the V_xN_y layer and the V_xN_yO_z layer is formed on the insulation layer and a surface of the metal line forming region, wherein the V layer, the V_xN_y layer and the V_xN_yO_z are formed on a surface of the insulation layer in sequence; and

forming a metal layer on the diffusion barrier in the metal line forming region.

9. The method according to claim 8, wherein the V layer is formed to have a thickness in the range of 10˜

100 Å

.

10. The method according to claim 8, wherein the V layer is formed through PVD or CVD.

11. The method according to claim 8, wherein the V layer is formed through CVD, and the CVD is conducted using V(NMe₂)₄ in the range of 10˜

100 sccm as source gas.

12. The method according to claim 8, wherein the V layer is formed through CVD, and the CVD is conducted at a temperature in the range of 200˜

500°

C. under pressure in the range of 0.1˜

10 Torr.

13. The method according to claim 8, wherein the V_xN_y layer is formed as a layer in which x has a range of 0.8˜

0.95 and y has a range of 0.05˜

0.2.

14. The method according to claim 8, wherein the V_xN_y layer is formed to have a thickness in the range of 5˜

50 Å

.

15. The method according to claim 8, wherein the V_xN_y layer is formed through any one of PVD, CVD and ALD.

16. The method according to claim 8, wherein the V_xN_y layer is formed through CVD, and the CVD is conducted using V(NMe₂)₄ and NH₃ each having an amount in the range of 10˜

100 sccm as source gas.

17. The method according to claim 8 wherein the V_xN_y layer is formed through CVD, and the CVD is conducted at a temperature in the range of 200˜

500°

C. under pressure in the range of 0.1˜

10 Torr.

18. The method according to claim 8, wherein the V_xN_y layer is formed through ALD, and the ALD is conducted by alternately supplying V(NMe₂)₄ and NH₃ each having an amount in the range of 10˜

100 sccm as source gas.

19. The method according to claim 8, wherein the V_xN_y layer is formed through ALD, and the ALD is conducted at a temperature in the range of 200˜

500°

C. under pressure in the range of 0.1˜

10 Torr.

20. The method according to claim 8, wherein the V_xN_y layer is formed by nitriding a surface of the V layer.

21. The method according to claim 8, wherein the V_xN_yO_z layer is formed as a layer in which x has a range of 0.7˜

0.94, y has a range of 0.05˜

0.2, and z has a range of 0.01˜

0.1.

22. The method according to claim 8, wherein the V_xN_yO_z layer is formed to have a thickness in the range of 5˜

50 Å

.

23. The method according to claim 8, wherein oxidation of the V_xN_y layer is conducted by annealing the V_xN_y layer under an oxygen atmosphere or plasma-processing the V_xN_y layer.

24. The method according to claim 8, wherein the metal layer comprises a copper layer, and the metal layer is formed to fill the metal line forming region.

25. The method according to claim 20, wherein nitridation of the V layer is conducted by annealing the V layer under a nitrogen atmosphere or plasma-processing the V layer.

26. The method according to claim 20, wherein nitridation of the V layer is conducted by annealing the V layer, and the annealing is conducted using N₂ in the range of 10˜

1,000 sccm.

27. The method according to claim 20, wherein nitridation of the V layer is conducted by annealing the V layer, and the annealing is conducted at a temperature in the range of 200˜

500°

C.

28. The method according to claim 20, wherein the nitridation of the V layer is conducted by plasma-processing the V-layer, and the plasma processing is conducted using N₂ in the range of 10˜

500 sccm.

29. The method according to claim 20, wherein the nitridation of the V layer is conducted by plasma-processing the V-layer, and the plasma processing is conducted at a temperature in the range of 200˜

500°

C. under pressure in the range of 1˜

10 Torr.

30. The method according to claim 20, wherein the nitridation of the V layer is conducted by plasma-processing the V-layer, and the plasma processing is conducted with RF power in the range of 100˜

1,000W.