Method for integrating trench MOS Schottky barrier devices into integrated circuits and related semiconductor devices

• US 7,741,693 B1
• Filed: 11/16/2007
• Issued: 06/22/2010
• Est. Priority Date: 11/16/2007
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Dyer, Terry
• Primary Examiner(s): Pham; Thanh V
• Assistant Examiner(s): FERNANDES, ERROL V
• Application Number:
  US11/985,628
• Time in Patent Office: 949 Days
• Field of Search: 257/197, 257/256, 257/328, 257/330, 257/335, 257/365, 257/417, 257/471, 257/476, 257/484, 257/260, 438/424, 438/527, 438/92
• US Class Current: 257/484
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/095 the components being Schottky barrier gate field-effect transistors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Trenches are formed in a semiconductor substrate, where the trenches include an outer trench and multiple inner trenches within the outer trench. A metal-oxide semiconductor (MOS) device and a trench MOS Schottky barrier (TMBS) device are also formed in the semiconductor substrate using the trenches. The MOS device could include the outer trench, and the TMBS device could include the inner trenches. At least one of the inner trenches may contact the outer trench, and/or at least one of the inner trenches may be electrically isolated from the outer trench. The MOS device could represent a trench vertical double-diffused metal-oxide semiconductor (VDMOS) device, and the TMBS device may be monolithically integrated with the trench VDMOS device in the semiconductor substrate. A guard ring that covers portions of the inner trenches and that is open over other portions of the inner trenches could optionally be formed in the semiconductor substrate.

Claims

1. A method comprising:

forming a plurality of trenches in a semiconductor substrate, the plurality of trenches including an outer trench and a plurality of inner trenches within the outer trench;

forming a metal-oxide semiconductor (MOS) device and a trench MOS Schottky barrier (TMBS) device in the semiconductor substrate using the plurality of trenches; and

forming a guard ring that covers portions of the inner trenches, the guard ring open over other portions of the inner trenches.

2. The method of claim 1, wherein at least one of the inner trenches contacts the outer trench.

3. The method of claim 1, wherein at least one of the inner trenches is electrically isolated from the outer trench.

4. The method of claim 1, wherein:

the outer trench forms a ring around the inner trenches;

each of the inner trenches is rectangular; and

portions of the substrate separate each of the inner trenches from the outer trench and each of the inner trenches from the other inner trenches.

5. The method of claim 4, wherein:

the substrate between the inner trenches comprises a p-type extension implant formed in an s-type epitaxial layer; and

the substrate around the outer trench comprises at least one n+ or p+ doped region in a p-type body in the substrate.

6. The method of claim 1, further comprising:

forming a plurality of deep doped regions in the substrate, the deep doped regions around the trenches.

7. The method of claim 1, wherein:

the MOS device comprises a trench vertical double-diffused metal-oxide semiconductor (VDMOS) device; and

the TMBS device is monolithically integrated with the trench VDMOS device.

8. The method of claim 1, wherein the guard ring is formed by performing a p+ implantation.

9. An integrated circuit comprising:

a semiconductor substrate;

a metal-oxide semiconductor (MOS) device monolithically integrated with a trench MOS Schottky barrier (TMBS) device, the MOS device and the TMBS device comprising a plurality of trenches in the semiconductor substrate, the plurality of trenches including an outer trench and a plurality of inner trenches within the outer trench; and

a guard ring covering portions of the inner trenches, the guard ring open over other portions of the inner trenches.

10. The integrated circuit of claim 9, wherein at least one of the inner trenches contacts the outer trench.

11. The integrated circuit of claim 9, wherein at least one of the inner trenches is electrically isolated from the outer trench.

12. The integrated circuit of claim 9, wherein:

the outer trench forms a ring around the inner trenches;

each of the inner trenches is rectangular; and

portions of the substrate separate each of the inner trenches from the outer trench and each of the inner trenches from the other inner trenches.

13. The integrated circuit of claim 12, wherein:

the substrate between the inner trenches comprises a p-type extension implant formed in an n-type epitaxial layer; and

the substrate around the outer trench comprises at least one n+ or p+ doped region in a p-type body in the substrate.

14. The integrated circuit of claim 9, wherein the substrate comprises a plurality of deep doped regions around the trenches.

15. The integrated circuit of claim 9, wherein:

the MOS device comprises a trench vertical double-diffused metal-oxide semiconductor (VDMOS) device; and

the TMBS device is monolithically integrated with the trench VDMOS device.

16. The integrated circuit of claim 9, wherein the guard ring comprises a p+ dopant.

17. An integrated circuit comprising:

a semiconductor substrate;

a vertical double-diffused metal-oxide semiconductor (VDMOS) device formed in a portion of the substrate, the VDMOS device comprising an outer trench ring in the substrate; and

a trench MOS Schottky barrier (TMBS) device formed in another portion of the substrate, the TMBS device comprising a plurality of inner trenches surrounded by the outer trench ring in the substrate, the inner trenches electrically isolated from the outer trench ring.

18. The integrated circuit of claim 17, wherein:

the outer trench ring is rectangular;

each of the inner trenches is rectangular; and

portions of the substrate separate each of the inner trenches from the outer trench ring and each of the inner trenches from the other inner trenches.

19. The integrated circuit of claim 18, wherein:

the substrate between the inner trenches comprises a p-type extension implant formed in an n-type epitaxial layer; and

the substrate around the outer trench ring comprises at least one n+ or p+ doped region in a p-type body in the substrate.

20. The integrated circuit of claim 17, further comprising a guard ring that covers portions of the inner trenches, the guard ring open over other portions of the inner trenches.