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Post last wiring level inductor using patterned plate process

  • US 7,741,698 B2
  • Filed: 07/16/2008
  • Issued: 06/22/2010
  • Est. Priority Date: 07/27/2005
  • Status: Expired due to Fees
First Claim
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1. A semiconductor structure, comprising:

  • a substrate having a metal wiring level within the substrate;

    a capping layer on and above a top surface of the substrate;

    a photo-imagable layer on and above a top surface of the capping layer, wherein the photo-imagable layer consists of a photo-imagable material;

    an inductor comprising a first portion in and above the photo-imagable layer and a second portion only above the photo-imagable layer, wherein a bottom surface of the photo-imagable layer is in direct mechanical contact with the top surface of the capping layer, and wherein a top surface of the photo-imagable layer is in direct mechanical contact with a bottom surface of the second portion of the inductor; and

    a wire bond pad, wherein a first portion of the wire bond pad is within the photo-imagable layer, wherein a second portion of the wire bond pad is above the photo-imagable layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the photo-imagable layer, wherein a second direction is orthogonal to the first direction, wherein a top surface of the first part of the first portion of the inductor and a top surface of the second portion of the inductor are coplanar, and wherein a height of the first part of the first portion of the inductor in the first direction is equal to a height of the second portion of the inductor in the first direction.

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