Metal line of semiconductor device and method of fabricating the same

• US 7,741,717 B2
• Filed: 06/29/2007
• Issued: 06/22/2010
• Est. Priority Date: 07/05/2006
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Hong, Young Ok, Lee, Dong Hwan
• Primary Examiner(s): MANDALA, MICHELLE
• Application Number:
  US11/771,214
• Publication Number:
  US 20080014734A1
• Time in Patent Office: 1,089 Days
• Field of Search: 257314-316, 257/203, 257/208, 257/211, 257/758, 257/774, 257/E29.129, 257/E29.3, 257/E21.179, 257/E21.422, 257/E21.68, 438/201, 438/211, 438/257, 438/593, 438/618, 438/622, 438/FOR.203, 438/FOR.355
• US Class Current: 257/758
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A metal line of a semiconductor device comprising contact plugs, a plurality of first trenches, first metal lines, a plurality of second trenches, and second metal lines. The contact plugs are formed over a semiconductor substrate and are insulated from each other by a first insulating layer. The plurality of first trenches are formed in the first insulating layer and are connected to first contact plugs of the contact plugs. The first metal lines are formed within the first trenches and are connected to the first contact plugs. The plurality of second trenches are formed over the first metal lines and the first insulating layer and comprise a second insulating layer connected to second contact plugs of the contact plugs. The second metal lines are formed within the second trenches and are connected to the second contact plugs.

Claims

1. A metal line of a semiconductor device comprising:

contact plugs formed over a semiconductor substrate and insulated from each other by a first insulating layer;

a plurality of first trenches formed in the first insulating layer and connected to first contact plugs of the contact plugs, which belong to one of an odd-numbered group and an even-numbered group;

first metal lines formed within the first trenches and connected to the first contact plugs;

a plurality of second trenches formed over the first metal lines and the first insulating layer and comprising a second insulating layer connected to second contact plugs of the contact plugs, which belong to the other of the odd-numbered group and the even-numbered group; and

second metal lines formed within the second trenches and connected to the second contact plugs.

2. The metal line of claim 1, wherein the contact plugs comprise drain contact plugs of a NAND flash memory device and are arranged in a line.

3. The metal line of claim 1, wherein the first metal lines comprise odd bit lines of a NAND flash memory device and the second metal lines comprise even bit lines, or the first metal lines comprise the even bit lines and the second metal lines comprise the odd bit lines.

4. The metal line of claim 1, wherein the first metal lines and the second metal lines are connected to a plurality of page buffers.

5. The metal line of claim 1, wherein a sum of a height of the first contact plug and a height of the first metal line is identical to a height of the second contact plug.

6. A metal line of a semiconductor device comprising:

contact plugs formed over a semiconductor substrate and insulated from each other by a first insulating layer;

a plurality of first metal lines formed in the first insulating layer and connected to first contact plugs of the contact plugs, which belong to one of an odd-numbered group and an even-numbered group;

a plurality of conductive layers formed over second contact plugs, which belong to the other of the odd-numbered group and the even-numbered group of the contact plugs;

forming a second insulating layer over the first insulating layer between the first metal lines and the conductive layers; and

a plurality of second metal lines formed over the second insulating layer and electrically connected to the conductive layers.

7. The metal line of claim 6, wherein the contact plugs comprise drain contact plugs of a NAND flash memory device and are arranged in a line.

8. The metal line of claim 6, wherein the first metal lines comprise odd bit lines of a NAND flash memory device and the second metal lines comprise even bit lines, or the first metal lines comprise the even bit lines and the second metal lines comprise the odd bit lines.

9. The metal line of claim 6, wherein the first metal lines and the second metal lines are connected to a plurality of page buffers.

10. The metal line of claim 6, wherein the conductive layer extends from on the first contact plugs to on the first insulating layer and has a width wider than the first contact plugs.

11. A method of forming metal lines of a semiconductor device, comprising:

providing a semiconductor substrate in which contact plugs insulated by a first insulating layer are formed;

forming first trenches connected to first contact plugs of the contact plugs, which belong to one of an odd-numbered group and an even-numbered group, in the first insulating layer;

forming first metal lines within the first trenches;

forming a second insulating layer over the first insulating layer comprising the first metal lines;

forming second trenches in the second insulating layer so that second contact plugs of the contact plugs, which belong to the other of the odd-numbered group and the even-numbered group, are exposed; and

forming second metal lines in the second trenches.

12. The method of claim 11, wherein the contact plugs comprise drain contact plugs of a NAND flash memory device and are arranged in a line.

13. The method of claim 11, wherein the first metal lines comprise odd bit lines of a NAND flash memory device and the second metal lines comprise even bit lines, or the first metal lines comprise the even bit lines and the second metal lines comprise the odd bit lines.

14. The method of claim 11, wherein a sum of a height of the first contact plug and a height of the first metal line is identical to a height of the second contact plug.

15. The method of claim 11, wherein a plurality of flash memory cells are formed in the semiconductor substrate.

16. A method of forming metal lines of a semiconductor device, comprising:

providing a semiconductor substrate in which contact plugs insulated by a first insulating layer are formed;

forming a conductive layer over first contact plugs of the contact plugs, which belong to one of an odd-numbered group and an even-numbered group, and forming first metal lines connected to second contact plugs, which belong to the other of the odd-numbered group and the even-numbered group, over the first insulating layer;

forming a second insulating layer over the first insulating layer between the conductive layer and the first metal lines; and

forming second metal lines connected to the conductive layer over the second insulating layer.

17. The method of claim 16, wherein the contact plugs comprise drain contact plugs of a NAND flash memory device and are arranged in a line.

18. The method of claim 16, wherein the first metal lines comprise odd bit lines of a NAND flash memory device and the second metal lines comprise even bit lines, or the first metal lines comprise the even bit lines and the second metal lines comprise the odd bit lines.

19. The method of claim 16, wherein the conductive layer extends from on the first contact plugs to on the first insulating layer and has a width wider than the first contact plugs.

20. The method of claim 16, wherein a plurality of flash memory cells are formed in the semiconductor substrate.