Frequency multiplier
First Claim
Patent Images
1. A device for modifying an input signal having an input signal frequency and a duty cycle, comprising:
- a clock that outputs a clock signal at a clock frequency;
a pulse counter that receives the clock signal and the input signal, wherein the pulse counter determines a first low pulse count corresponding to the input signal being at a low state and a first high pulse count corresponding to the input signal being at a high state;
a count divider that modifies the first low pulse count to obtain a divided first low pulse count and that modifies the first high pulse count to obtain a divided first high pulse count;
a low pulse counter that receives the clock signal, wherein the low pulse counter determines a second low pulse count corresponding to the input signal being at the low state;
a high pulse counter that receives the clock signal, wherein the high pulse counter determines a second high pulse count corresponding to the input signal being at the high state;
a low pulse comparator that compares the divided first low pulse count with the second low pulse count, wherein the low pulse comparator outputs a low pulse comparison signal when the divided first low pulse count and the second low pulse count are equal;
a high pulse comparator that compares the divided first high pulse count with the second high pulse count, wherein the high pulse comparator outputs a high pulse comparison signal when the divided first high pulse count and the second high pulse count are equal; and
an output module that receives the low pulse comparison signal and high pulse comparison signal and outputs an output signal having the duty cycle of the input signal and an output signal frequency that is a multiple of the input signal frequency.
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Abstract
A device for modifying an input signal having an input signal frequency and a duty cycle is disclosed. The device determines two separate counts for each of the high and low pulses of the input signal. One of the two counts for each of the high and low pulses is divided. The divided count is then compared with the undivided count. Based on this comparison, an output module outputs an output signal that has the same duty cycle as the input signal but at a frequency that is a multiple of the input signal frequency.
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Citations
20 Claims
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1. A device for modifying an input signal having an input signal frequency and a duty cycle, comprising:
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a clock that outputs a clock signal at a clock frequency; a pulse counter that receives the clock signal and the input signal, wherein the pulse counter determines a first low pulse count corresponding to the input signal being at a low state and a first high pulse count corresponding to the input signal being at a high state; a count divider that modifies the first low pulse count to obtain a divided first low pulse count and that modifies the first high pulse count to obtain a divided first high pulse count; a low pulse counter that receives the clock signal, wherein the low pulse counter determines a second low pulse count corresponding to the input signal being at the low state; a high pulse counter that receives the clock signal, wherein the high pulse counter determines a second high pulse count corresponding to the input signal being at the high state; a low pulse comparator that compares the divided first low pulse count with the second low pulse count, wherein the low pulse comparator outputs a low pulse comparison signal when the divided first low pulse count and the second low pulse count are equal; a high pulse comparator that compares the divided first high pulse count with the second high pulse count, wherein the high pulse comparator outputs a high pulse comparison signal when the divided first high pulse count and the second high pulse count are equal; and an output module that receives the low pulse comparison signal and high pulse comparison signal and outputs an output signal having the duty cycle of the input signal and an output signal frequency that is a multiple of the input signal frequency. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A device for modifying an input signal having an input signal frequency and a duty cycle, comprising:
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a clock that outputs a clock signal at a clock frequency; a frequency divider that modifies the clock signal to obtain a divided frequency clock signal; a pulse counter that receives the divided frequency clock signal and the input signal, wherein the pulse counter determines a divided low pulse count corresponding to the input signal being at a low state and a divided high pulse count corresponding to the input signal being at a high state; a low pulse counter that receives the clock signal, wherein the low pulse counter determines a low pulse count corresponding to the input signal being at the low state; a high pulse counter that receives the clock signal, wherein the high pulse counter determines a high pulse count corresponding to the input signal being at the high state; a low pulse comparator that compares the divided low pulse count with the low pulse count, wherein the low pulse comparator outputs a low pulse comparison signal when the divided low pulse count and the low pulse count are equal; a high pulse comparator that compares the divided high pulse count with the high pulse count, wherein the high pulse comparator outputs a high pulse comparison signal when the divided high pulse count and the high pulse count are equal; and an output module that receives the low pulse comparison signal and high pulse comparison signal and outputs an output signal having the duty cycle of the input signal and an output signal frequency that is a multiple of the input signal frequency. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method for modifying an input signal having an input signal frequency and a duty cycle, comprising:
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providing a clock signal at a clock frequency; determining a divided low pulse count corresponding to the input signal being at a low state; determining a divided high pulse count corresponding to the input signal being at a high state; determining a low pulse count corresponding to the input signal being at the low state; determining a high pulse count corresponding to the input signal being at the high state; comparing the divided low pulse count with the low pulse count; comparing the divided high pulse count with the high pulse count; outputting a low pulse comparison signal when the divided low pulse count and the low pulse count are equal; outputting a high pulse comparison signal when the divided high pulse count and the high pulse count are equal; and outputting an output signal having the duty cycle of the input signal and an output signal frequency that is a multiple of the input signal frequency based on the high pulse comparison signal and the low pulse comparison signal. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification