Dual-use comparator/op amp for use as both a successive-approximation ADC and DAC

• US 7,741,981 B1
• Filed: 12/30/2008
• Issued: 06/22/2010
• Est. Priority Date: 12/30/2008
• Status: Active Grant

• Current Assignee: Hong Kong Applied Science And Technology Research Institute Co., Ltd.
• Original Assignee: Hong Kong Applied Science And Technology Research Institute Co., Ltd.
• Inventors: Wan, Ho Ming Karen, Kwong, Kwok Kuen David, Wong, Yat To William, Wu, Tin Ho Andy, Yau, Hok Mo, Chan, Kwai Chi
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US12/345,844
• Publication Number:
  US 20100164761A1
• Time in Patent Office: 539 Days
• Field of Search: 341/108, 341/110, 341/155, 341/144
• US Class Current: 341/110
• CPC Class Codes: H03M 1/02 Reversible analogue/digital converters
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.

Claims

1. A dual-use analog-digital converter comprising:

a charge-sharing line;

a plurality of switches controlled by a digital value;

an array of capacitors having weighted capacitance values, wherein array capacitors in the array connect to the charge-sharing line and to the plurality of switches;

an analog input having an analog input voltage,

a fixed voltage;

wherein the digital value controls the plurality of switches to selectively connect array capacitors to the analog input voltage and to the fixed voltage;

a terminal capacitor connected to the charge-sharing line, wherein charge is shared between the array capacitors and the terminal capacitor to generate a first compare voltage;

a re-configurable comparator stage that receives the first compare voltage and compares the first compare voltage to a second comparator input to generate a compare output and to generate a feedback output;

a feedback switch that connects the feedback output to the second comparator input during a digital-to-analog converter (DAC) mode, and isolates the feedback output from the second comparator input during an Analog-to-Digital Converter (ADC) mode;

an ADC switch that connects the second comparator input to a second compare voltage during the ADC mode, and isolates the second comparator input from the second compare voltage during the DAC mode;

control logic for adjusting the digital value to the plurality of switches during a sequence of compare operations, and for examining the compare output from the re-configurable comparator stage during the sequence of compare operations to determine a final digital value that represents the analog input voltage;

wherein the first compare voltage generated by the array of capacitors on the charge-sharing line is compared to the second compare voltage by the re-configurable comparator stage during the ADC mode to generate the compare output when determining the final digital value that represents the analog input voltage; and

a digital input receiving a digital input value, wherein the control logic applies the digital input value to the plurality of switches as the digital value during the DAC mode, wherein the re-configurable comparator stage generates an analog output represented by the digital input value during the DAC mode,

whereby the re-configurable comparator stage and the array of capacitors are used both for analog-to-digital conversion and for digital-to-analog conversion.

2. The dual-use analog-digital converter of claim 1 further comprising:

a Successive-Approximation-Register (SAR) that stores the digital value, wherein the control logic updates the digital value in the SAR during the sequence of compare operations and outputs the digital value from the SAR as the final digital value at an end of the sequence of compare operations.

3. The dual-use analog-digital converter of claim 1 wherein each switch in the plurality of switches comprises a 3-way switch that selectively connects one of the array capacitors to the analog input voltage, to a ground voltage, and to a reference voltage in response to a bit in the digital value;

wherein the fixed voltage comprises two fixed voltages, the ground voltage and the reference voltage.

4. The dual-use analog-digital converter of claim 1 wherein the re-configurable comparator stage comprises:

a differential pre-amplifier having a first differential input that receives the first compare voltage from the charge-sharing line and having a second differential input that receives the second comparator input, the differential pre-amplifier comparing the first compare voltage to a voltage on the second comparator input to generate an intermediate output;

a differential latch receiving a differential latch input, the differential latch having a bi-stable triggered by the differential latch input to store a latched value, the differential latch generating the compare output from the bi-stable;

a differential amplifier receiving a differential amp input, the differential amplifier generating the feedback output to the feedback switch in response to the differential amp input;

a first intermediate switch that connects the intermediate output to the differential latch input during the ADC mode, and isolates the intermediate output from the differential latch input during the DAC mode; and

a second intermediate switch that connects the intermediate output to the differential amp input during the DAC mode, and isolates the intermediate output from the differential amp input during the ADC mode.

5. The dual-use analog-digital converter of claim 4 wherein the first intermediate switch is a differential pair of switches that comprise a true switch that switches a true signal in the intermediate output, and a complement switch that switches a complement signal in the intermediate output;

wherein the second intermediate switch is a differential pair of switches that comprise a true switch that switches a true signal in the intermediate output, and a complement switch that switches a complement signal in the intermediate output.

6. The dual-use analog-digital converter of claim 5 wherein the differential pre-amplifier further comprises:

a first differential transistor having a gate receiving the first compare voltage;

a second differential transistor having a gate receiving the second comparator input;

a first switched current sink resistance;

a second switched current sink resistance;

a first gain switch that connects the first differential transistor to the first switched current sink resistance during the ADC mode, and isolates the first differential transistor from the first switched current sink resistance during the DAC mode; and

a second gain switch that connects the second differential transistor to the second switched current sink resistance during the ADC mode, and isolates the second differential transistor from the second switched current sink resistance during the DAC mode;

whereby gain is increased by connecting the first switched current sink resistance and the second switched current sink resistance during the ADC mode.

7. The dual-use analog-digital converter of claim 6 wherein the array of capacitors comprises 16 array capacitors having binary-weighted capacitance values;

wherein capacitance values of the array capacitors are 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1K, 2K, 4K, 8K, 16K, and 32K times a smallest capacitance value, wherein K is 1024.

8. The dual-use analog-digital converter of claim 7 wherein the terminal capacitor has a capacitance value substantially equal to a smallest capacitance value for array capacitors in the array of capacitors.

9. The dual-use analog-digital converter of claim 1 further comprising:

a second charge-sharing line connected to the ADC switch and carrying the second compare voltage;

a plurality of second switches controlled by a second digital value;

a second array of capacitors having weighted capacitance values, wherein second array capacitors in the second array connect to the second charge-sharing line and to the plurality of second switches;

a second analog input having a second analog input voltage,

wherein the second digital value controls the plurality of second switches to selectively connect second array capacitors to the second analog input voltage and to the fixed voltage; and

a second terminal capacitor connected to the second charge-sharing line, wherein charge is shared between the second array capacitors and the second terminal capacitor to generate the second compare voltage.

10. The dual-use analog-digital converter of claim 9 wherein the second analog input connects to a reference voltage;

wherein the analog input and the second analog input connect to a differential analog input.

11. A reversible analog-digital converter comprising:

an analog input;

a digital input;

a charge-sharing line;

a plurality of switches controlled by digital bits that indicate when to connect to the analog input and when to connect to a fixed voltage;

a plurality of capacitors having differing capacitance values and each having a terminal connected to the charge-sharing line and another terminal connected to a switch in the plurality of switches;

control logic that generates the digital bits from the digital input when operating in a Digital-to-Analog Converter (DAC) mode, and that generates a sequence of the digital bits to cause the plurality of switches to adjust voltages applied to the plurality of capacitors to vary a voltage of the charge-sharing line to test a sequence of digital values during an Analog-to-Digital Converter (ADC) mode to determine a final digital value that represents a voltage of the analog input;

a re-configurable comparator stage that comprises;

a differential pre-amplifier having a first differential input connected to the charge-sharing line and a second differential input, for generating a differential intermediate output;

a first intermediate switch that connects the differential intermediate output to a differential latch input during the ADC mode, and isolates the differential intermediate output from the differential latch input during the DAC mode;

a second intermediate switch that connects the differential intermediate output to a differential amp input during the DAC mode, and isolates the differential intermediate output from the differential amp input during the ADC mode;

a differential latch that receives the differential intermediate output from the first intermediate switch and stores a compare value determined by the differential intermediate output;

wherein the compare value is applied to the control logic to determine a portion of the final digital value during ADC mode;

a differential amplifier that receives the differential intermediate output from the second intermediate switch during DAC mode and buffers the differential intermediate output to generate a DAC output; and

a feedback switch that connects the DAC output to the second differential input during the DAC mode, and isolates the DAC output from the second differential input during the ADC mode;

wherein the DAC output is an analog output voltage that represents the digital input when operating in the DAC mode,

whereby the plurality of capacitors and the re-configurable comparator stage are used both for conversion to analog an conversion to digital.

12. The reversible analog-digital converter of claim 11 wherein the differential pre-amplifier comprises:

a current source that generates a source current;

a first differential transistor having a gate that receives the first differential input which controls conducting a portion of the source current to a first differential intermediate output node of the differential intermediate output;

a first resistor;

a first switch that connects the first resistor to the first differential intermediate output node during the ADC mode, and isolates the first differential intermediate output node from the first resistor during the DAC mode;

a second differential transistor having a gate that receives the second differential input which controls conducting a portion of the source current to a second differential intermediate output node of the differential intermediate output;

a second resistor; and

a second switch that connects the second resistor to the second differential intermediate output node during the ADC mode, and isolates the second differential intermediate output node from the second resistor during the DAC mode,

whereby the first resistor and the second resistor are switched during ADC mode to adjust gain of the differential pre-amplifier.

13. The reversible analog-digital converter of claim 12 further comprising:

a second charge-sharing line;

a second analog input;

a plurality of second switches controlled by digital bits that indicate when to connect to the second analog input and when to connect to the fixed voltage;

a plurality of second capacitors having differing capacitance values and each having a terminal connected to the second charge-sharing line and another terminal connected to a second switch in the plurality of second switches; and

an ADC switch that connects the second charge-sharing line to the second differential input to the differential pre-amplifier during the ADC mode, and isolates the second differential input from the differential pre-amplifier during the DAC mode.

14. The reversible analog-digital converter of claim 13 wherein the fixed voltage is a reference voltage or a ground voltage.

15. The reversible analog-digital converter of claim 12 wherein the differential amplifier comprises:

a first p-channel bias transistor having a gate receiving a first bias voltage;

a first p-channel cascode transistor, in series with the first p-channel bias transistor, having a gate receiving a first cascode bias voltage and a drain generating the first bias voltage;

a first n-channel cascode transistor, in series with the first p-channel cascode transistor, having a gate receiving a second cascode bias voltage and a drain generating the first bias voltage;

a first n-channel bias transistor having a gate receiving a second bias voltage, and a drain connected to the first n-channel cascode transistor, wherein the drain is also connected to the first differential intermediate output node through the second intermediate switch during the DAC mode;

a second p-channel bias transistor having a gate receiving a second bias voltage;

a second p-channel cascode transistor, in series with the second p-channel bias transistor, having a gate receiving the second cascode bias voltage and a drain connected to a first output gate node;

a p-channel compensating transistor having a gate and a drain connected to a compensating node and a source connected to the first output gate node;

an n-channel compensating transistor having a gate and a drain connected to the compensating node and a source connected to a second output gate node;

a second n-channel cascode transistor, in series with the second p-channel cascode transistor, having a gate receiving the second cascode bias voltage and a drain connected to the second output gate node;

a second n-channel bias transistor having a gate receiving the second bias voltage, and a drain connected to the second n-channel cascode transistor, wherein the drain is also connected to the second differential intermediate output node through the second intermediate switch during the DAC mode;

a p-channel output transistor having a gate receiving the first output gate node and a drain driving the DAC output and a source connected to a power supply;

an n-channel output transistor having a gate receiving the second output gate node and a drain driving the DAC output and a source connected to a ground; and

a compensating capacitor connected between the DAC output and the compensating node.

16. The reversible analog-digital converter of claim 13 wherein the differential latch comprises:

a first differential latch transistor having a gate connected by the first intermediate switch to the differential intermediate output during the ADC mode, and a drain connected to a first bistable node;

a first cross-coupled transistor having a drain connected to the first bistable node and a gate connected to a second bistable node;

a first mirror transistor having a gate connected to the first bistable node, for generating a first minor current;

a second differential latch transistor having a gate connected by the second intermediate switch to the differential intermediate output during the ADC mode, and a drain connected to the second bistable node;

a second cross-coupled transistor having a drain connected to the second bistable node and a gate connected to the first bistable node;

a second mirror transistor having a gate connected to the second bistable node, for generating a second mirror current;

a first output cascode transistor having a drain generating the compare value on a compare output, and having a gate receiving a first cascode bias voltage, and a channel passing the second minor current; and

a second output cascode transistor having a drain generating the compare value on the compare output, and having a gate receiving a second cascode bias voltage, and a channel passing the second minor current.

17. A dual-direction analog-digital converter comprising:

an first analog input having a first analog input voltage,

a second analog input having a second analog input voltage,

a digital input receiving a digital input value;

a fixed voltage;

a first charge-sharing line;

first switch means for switching voltages in response to a digital value;

first array means for storing charge using weighted capacitance values of first capacitors, wherein each first capacitor is connected to the first charge-sharing line and to a plurality of the first switch means;

wherein the digital value controls the first switch means to selectively connect first capacitors to the first analog input voltage and to the fixed voltage;

first terminal capacitor means for sharing charge from the first charge-sharing line, wherein charge is shared between the first capacitors and the first terminal capacitor means to generate a first compare voltage;

a second charge-sharing line;

second switch means for switching voltages in response to a second digital value;

second array means for storing charge using weighted capacitance values of second capacitors, wherein each second capacitor is connected to the second charge-sharing line and to a plurality of the second switch means;

wherein the second digital value controls the second switch means to selectively connect second capacitors to the second analog input voltage and to the fixed voltage;

second terminal capacitor means for sharing charge from the second charge-sharing line, wherein charge is shared between the second capacitors and the second terminal capacitor means to generate a second compare voltage;

re-configurable means, receiving the first compare voltage, for comparing the first compare voltage to a second comparator input to generate a compare output and to generate a feedback output;

feedback switch means for connecting the feedback output to the second comparator input during a digital-to-analog converter (DAC) mode, and for isolating the feedback output from the second comparator input during an Analog-to-Digital Converter (ADC) mode;

ADC switch means for connecting the second comparator input to a second compare voltage during the ADC mode, and for isolating the second comparator input from the second compare voltage during the DAC mode;

control logic means for adjusting the digital value and the second digital value during a sequence of compare operations during ADC mode, and for examining the compare output from the re-configurable means during the sequence of compare operations to determine a final digital value that represents a combination of the first analog input voltage and the second analog input voltage, and for applying the digital input value to the plurality of first switch means as the digital value during the DAC mode, wherein the re-configurable means generates an analog output represented by the digital input value during the DAC mode,

whereby the re-configurable means and the first array means of first capacitors are used both for analog-to-digital conversion and for digital-to-analog conversion.

18. The dual-direction analog-digital converter of claim 17 further comprising:

Successive-Approximation-Register (SAR) means for storing the digital value, wherein the control logic means is further for updating the digital value in the SAR means during the sequence of compare operations and for outputting the digital value from the SAR means as the final digital value at an end of the sequence of compare operations.

19. The dual-direction analog-digital converter of claim 17 wherein the re-configurable means comprises:

differential pre-amplifier means, having a first differential input that receives the first compare voltage from the first charge-sharing line and having a second differential input that receives the second comparator input, for comparing the first compare voltage to a voltage on the second comparator input to generate an intermediate output;

differential latch means, receiving a differential latch input, for triggering a bi-stable in response to the differential latch input to store a latch value, the differential latch means also for generating the compare output from the bi-stable;

differential amplifier means, receiving a differential amp input, for generating the feedback output to the feedback switch means in response to the differential amp input;

first intermediate switch means for connecting the intermediate output to the differential latch input during the ADC mode, and for isolating the intermediate output from the differential latch input during the DAC mode; and

second intermediate switch means for connecting the intermediate output to the differential amp input during the DAC mode, and for isolating the intermediate output from the differential amp input during the ADC mode.

20. The dual-direction analog-digital converter of claim 17 wherein the dual-direction analog-digital converter is a block integrated on a System-On-a-Chip (SOC).